HDLBits: ece241 2013 q8

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 

    parameter IDLE = 3'b000;
    parameter BIT0 = 3'b001;
    parameter BIT1 = 3'b010;
    
    reg [2:0] state,next_state;
    
    always @(posedge clk or negedge aresetn)
        begin
            if(!aresetn)
                state <= IDLE;
            else
                state <= next_state;
        end
    
    always @(*)
        begin
            case(state)
                IDLE:
                    begin
                        if(x == 1'b0)
                            next_state <= IDLE;
                        else
                            next_state <= BIT0;
                    end
                BIT0:
                    begin
                        if(x == 1'b0)
                            next_state <= BIT1;
                        else
                            next_state <= BIT0;
                    end
                BIT1:
                    begin
                        if(x == 1'b0)
                            next_state <= IDLE;
                        else
                            next_state <= BIT0;
                    end
                default:
                    next_state <= IDLE;
            endcase
        end
     
        assign z = (state == BIT1) & x;

endmodule