保护你的源代码：生成VQM文件

最新推荐文章于 2023-11-20 15:20:47 发布

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最新推荐文章于 2023-11-20 15:20:47 发布

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保护你的源代码：生成VQM文件

1、将你的Verilog模块工程做如下图在工程Assigments->setting中设置,Save a node-level netlist....

2、Processing-->Start-->Start VQM Write生成atom_netlists目录下VQM文件

3、在其他新工程中放置<project directory>\atom_netlists\vqm文件，就可以使用了.

打开菜单project -〉implementation options -> implementation results
指定生成文件的目录，以及生成文件的名称( .vqm),综合完成后，就可以在指定的目录下找到对应的vqm文件

-----------------下面为Altera官网上的说明--------------------------------------

Verilog Quartus Mapping File (.vqm) Definition

An ASCII text file (with the extension .vqm) that contains an node-level (or atom) netlist. VQM files are typically generated by EDA synthesis tools such as Synplicity Synplify, and contain the logid for the design.

A VQM file can also be generated by the Quartus II Compiler in order to save synthesis results for the LogicLock Import / Export flow in one of the following ways:

Turn on Save a node-level netlist in the Compilation Process Settings page in the Settings dialog box, and then compile the design.
Turn on Save a node-level netlist in the Back-Annotate Assignments dialog box and back-annotate a design.
Click Start VQM Writer.

Altera recommends using the Incremental Compilation flow to preserve synthesis and fitting results in preference to the LogicLock Import / Export flow or back-annotation flow.

When generated from intermediate synthesis results in the Quartus II software, the VQM File is placed in the <project directory>\atom_netlists\ directory. You can then use the VQM File by creating and then compiling a new project from the file.

Altera recommends that you do not edit VQM Files.

转载至http://hi.baidu.com/fpga_cpld/item/ab61eff44f860cc5a935a241

另还可参考http://www.cnblogs.com/adamite/p/qxp_vqm.html