ZedBoard教程PL篇(3):vga显示彩条

开发板环境：vivado2017.4

开发板：Zedboard 芯片型号：xc7z020clg484-1

本章主要使用用verilog编写一个vga程序，然后使用vga接口显示一个彩条

VGA接口硬件连接

VGA程序代码

  VGA代码参考 虚无缥缈vs威武的，只是改了部分代码

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/02/27 16:01:26
// Design Name: 
// Module Name: vga_test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module vga_test(
	clock,
	reset,
	vga_hs,
	vga_vs,
	vga_r,
	vga_g,
	vga_b
);
 
input			clock;
input			reset;
output			vga_hs;
output			vga_vs;
output	[3:0]	vga_r;
output	[3:0]	vga_g;
output	[3:0]	vga_b;
 
 
 
 
parameter H_SYNC = 12'd44;
parameter H_BACK = 12'd148;
parameter H_ACTIVE = 12'd1920;
parameter H_FRONT = 12'd88;
parameter H_TOTAL = H_SYNC + H_BACK + H_ACTIVE + H_FRONT;
 
parameter V_SYNC = 12'd5;
parameter V_BACK = 12'd36;
parameter V_ACTIVE = 12'd1080;
parameter V_FRONT = 12'd4;
parameter V_TOTAL = V_SYNC + V_BACK + V_ACTIVE + V_FRONT;
 
 
reg	[11:0]	    hsync_cnt;
reg	[11:0]	    vsync_cnt;
wire			hsync_en;
wire			vsync_en;
wire			clk_148M;
reg	[23:0] 	    data_out;
reg	[4:0]		vga_r_reg;
reg	[5:0]		vga_g_reg;
reg	[4:0]		vga_b_reg;
 
  clk_wiz_0 instance_name
 (
  // Clock out ports
  .clk_out1(clk_148M),     // output clk_out1//148.5M
 // Clock in ports
  .clk_in1(clock));      // input clk_in1 //100M
 
 
//HSYNC计数
always@(posedge clk_148M or negedge reset)begin
		if(reset	==	1'b0)
			hsync_cnt	<=	12'd0;
		else	if(hsync_cnt == H_TOTAL -12'd1)
			hsync_cnt	<=	12'd0;
		else
			hsync_cnt	<=	hsync_cnt	+	1'b1;
end
 
//hsync
assign vga_hs = ((hsync_cnt >= 12'd0)&&(hsync_cnt < H_SYNC))? 1'b0:1'b1;
 
//VSYNC计数
always@(posedge clk_148M or negedge	reset)begin
		if(reset	==	1'b0)
			vsync_cnt	<=	12'd0;
		else if(hsync_cnt == H_TOTAL -12'd1)
			if(vsync_cnt == V_TOTAL - 12'd1)
				vsync_cnt	<=	12'd0;
		else
			vsync_cnt	<=	vsync_cnt	+	1'b1;
end
 
//vsync
assign vga_vs = ((vsync_cnt >= 12'd0)&&(vsync_cnt < V_SYNC))? 1'b0:1'b1;
 
//hsync和vsync显示有效区域
assign	hsync_en	=	((hsync_cnt >= (H_SYNC + H_BACK))&&(hsync_cnt < (H_SYNC + H_BACK + H_ACTIVE)));
assign	vsync_en	=	((vsync_cnt	>=	(V_SYNC + V_BACK))&&(vsync_cnt < (V_SYNC + V_BACK + V_ACTIVE)));
 
//方格
  always@(posedge clk_148M or negedge reset)begin
          if(!reset)
            data_out <=  24'd0;
          else if(hsync_en && vsync_en)
              case(hsync_cnt - H_SYNC - H_BACK)
                    0:        data_out <=  {8'h00,8'h00,8'h00};
                    240:      data_out <=  {8'h00,8'h00,8'hff};
                    480:      data_out <=  {8'h00,8'hff,8'h00};
                    720:      data_out <=  {8'h00,8'hff,8'hff};
                    960:      data_out <=  {8'hff,8'h00,8'h00};
                    1200:     data_out <=  {8'hff,8'h00,8'hff};
                    1440:     data_out <=  {8'hff,8'hff,8'h00};
                    1680:     data_out <=  {8'hff,8'hff,8'hff};
                    default:data_out <= data_out;
              endcase
          else
              data_out <=  24'd0;        
    end
 
assign	vga_r	=	(hsync_en && vsync_en)? data_out[23:20]: 4'd0;
assign	vga_g	=	(hsync_en && vsync_en)? data_out[15:12]: 4'd0;
assign	vga_b	=	(hsync_en && vsync_en)? data_out[7:4]: 4'd0;
 
 
 
endmodule

约束文件

set_property PACKAGE_PIN V20 [get_ports {vga_r[0]}]
set_property PACKAGE_PIN U20 [get_ports {vga_r[1]}]
set_property PACKAGE_PIN V19 [get_ports {vga_r[2]}]
set_property PACKAGE_PIN V18 [get_ports {vga_r[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[0]}]
set_property PACKAGE_PIN AB22 [get_ports {vga_g[0]}]
set_property PACKAGE_PIN AA22 [get_ports {vga_g[1]}]
set_property PACKAGE_PIN AB21 [get_ports {vga_g[2]}]
set_property PACKAGE_PIN AA21 [get_ports {vga_g[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[0]}]
set_property PACKAGE_PIN Y21 [get_ports {vga_b[0]}]
set_property PACKAGE_PIN Y20 [get_ports {vga_b[1]}]
set_property PACKAGE_PIN AB20 [get_ports {vga_b[2]}]
set_property PACKAGE_PIN AB19 [get_ports {vga_b[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[0]}]
set_property PACKAGE_PIN Y9 [get_ports clock]
set_property PACKAGE_PIN F22 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports clock]
set_property IOSTANDARD LVCMOS33 [get_ports reset]
set_property PACKAGE_PIN AA19 [get_ports vga_hs]
set_property PACKAGE_PIN Y19 [get_ports vga_vs]
set_property IOSTANDARD LVCMOS33 [get_ports vga_hs]
set_property IOSTANDARD LVCMOS33 [get_ports vga_vs]

vivado工程截图

​

 开发板硬件连接 

​

 VGA显示效果