verilog 简单module_简单的Verilog测试模板结构

//timescale

`timescale 1ns/1nsmoduletb_module();//the Internal motivation variable(register) and output wire//the External motivation storage variable//Sub module signal,example: wire [1:0] xxx == xxx_inst.xxx_inst.xxx;//Global variable initialization ,such as 'clk'、'rst_n'

initial begin#0 rst_n = 0;

clk= 0;

#25 rst_n = 1;end

//Internal motivation variable initialization//initial begin//end//cloclk signal generation

always #10 clk = ~clk ;//Cases of sub module xxxx xxxx_inst(.(),.(), ... ,.());//Internal motivation variable assignment using task or random/*example

task data_assign(xx); | task rand_bit();

integer xx,xx,...; | integer i;

begin | begin

for( ; ; )begin | for(i=0; i<255; i=i+1)begin

@(posedge clock) | @(posedge sclk);

Internal motivation variable <= xxxxx; | Internal motivation variable <={$random} %2;

end | end

end | end

endtask | endtask*/

endmodule