FIFO depth

One of the most interesting architectural decision in the design project is how to calculate the depth of a FIFO. FIFO is an intermediate logic where the data would be buffered or stored . Smaller FIFO depth can cause overflow scenario and cause a data loss.

For worst case scenario, difference in the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered for calculating the depth of the FIFO.

Any Asynchronous FIFO has a write frequency and a read frequency. Assume that the write frequency (Fw) is faster than read frequency (Fr).

Scenario 1 :

Fw = 1/Tw and Fr = 1/Tr where Tw and Tr are Time periods of write and read respectively.

Now Transmitter (Write side) wants to transmit "W" words of data. But FIFO can take only "N" words of data in Tw time.
Time taken to transmit "W" words is (Tw/N) * W

But Receiver can read "P" words in Tr time interval.
So the Receiver can read ((Tw/N)*W*P)/Tr words in (Tw/N) * W time .

Subtract the the data read from FIFO to the data written into the FIFO.
Here the data written into the FIFO is "W" words
Data read from the FIFO is ((Tw/N)*W*P)/Tr words.

FIFO size = W- ((Tw/N)*W*P)/Tr

Where

W = Maximum number of bytes that the transmitter can send
N = Number of bytes that the transmitter sends per Tw
Tw = Transmitter's time period
P = Number of bytes that receiver receives per Tr
Tr = Receiver's time period

Scenario 2 :

Consider the case of a FIFO where the 'Fw' is 100 MHz and 50 words are written into the FIFO in 100 clocks while the 'Fr' is 50 MHz and one word is read out every clock.

In the worst case scenario, the 50 words are written into the FIFO as a burst in 500 ns. In the same time duration, the read side can read only 25 words out of the FIFO. The remaining 25 words are read out of the FIFO in the 50 idle write clocks. So the depth of the FIFO should be at least 28. (Three clock cycles are for synchronizer latency).

转载于:https://www.cnblogs.com/zhangzhi/archive/2010/10/24/1859848.html

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Standard SPI Mode Standard SPI mode is selected when the Mode option in the Vivado IDE is set to Standard. The relevant parameters in this mode are: • Mode • Enable STARTUPE2 Primitive • Transaction Width • No. of Slaves • Frequency Ratio Send Feedback AXI Quad SPI v3.2 7 PG153 April 4, 2018 www.xilinx.com Chapter 1: Overview • Enable FIFO The properties of the core in standard SPI mode, including or excluding a FIFO, are described as: • The choice of inclusion of FIFO is based on the Enable FIFO parameter. FIFO Depth parameter is linked to Enable FIFO parameter. FIFO Depth limits the transmit and receive FIFO depth to 16 or 256 when FIFO is enabled. When FIFO is not enabled, the value of FIFO depth parameter is considered to be 0. A FIFO depth of 256 should be used because this is the most suitable depth in relation to the flash memory page size. • The valid values for the FIFO Depth option in this mode are 16 or 256 when FIFO is enabled through Enable FIFO parameter. When Enable FIFO is 0 and no FIFO is included in the core. Data transmission occurs through the single transmit and receive register. When FIFO Depth is 16 or 256, the transmit or receive FIFO is included in the design with a depth of 16 or 256 elements. The width of the transmit and receive FIFO is configured with the Transaction Width option. The AXI Quad SPI core supports continuous transfer mode. When configured as master, the transfer continues until the data is available in the transmit register/FIFO. This capability is provided in both manual and automatic slave select modes. As an example, during the page read command, the command, address, and number of data beats in the DTR must be set equal to the same number of data bytes intended to be read by the SPI memory. When the core is configured as a slave, if the slave select line (SPISEL) goes High (inactive state) during the data element transfer, the current transfer is aborted. If the slave select line goes Low, the aborted data element is transmitted again. The slave mode of the core is allowed only in the standard SPI mode.
07-22
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