序列检测器是时序数字电路设计中经典的教学范例,夏宇闻的《verilog数字系统设计教程》一书中有这个例子,用verilog设计一个“10010”序列的检测器。看完后我觉得F和G两个状态多余了,并且刚学了三段式状态机的写法,所以改写了这个程序,代码如下:
1
module
seqdet(nrst,clk,x,z);
2 input nrst,clk;
3 input x;
4 output z;
5 reg z;
6
7 reg [ 4 : 0 ]CS,NS;
8 parameter [ 4 : 0 ]
9 IDLE = 5 ' b00000,
10 A = 5 ' b00001,
11 B = 5 ' b00010,
12 C = 5 ' b00100,
13 D = 5 ' b01000,
14 E = 5 ' b10000;
15
16 always @( posedge clk or negedge nrst)
17 begin
18 if ( ! nrst)
19 CS <= IDLE;
20 else
21 CS <= NS;
22 end
23
24 always @(nrst or CS or x)
25 begin
26 NS = 5 ' bx;
27 case (CS)
28 IDLE: begin
29 if (x == 1 ) NS = A; else NS = IDLE; end
30 A: begin
31 if (x == 0 ) NS = B; else NS = A; end
32 B: begin
33 if (x == 0 ) NS = C; else NS = A; end
34 C: begin
35 if (x == 1 ) NS = D; else NS = IDLE; end
36 D: begin
37 if (x == 0 ) NS = E; else NS = A; end
38 E: begin
39 if (x == 0 ) NS = C; else NS = A; end
40 default :
41 NS = IDLE;
42 endcase
43 end
44
45 always @( posedge clk or negedge nrst)
46 begin
47 if ( ! nrst) z <= 1 ' b0;
48 else begin
49 z <= 1 ' b0;
50 case (NS)
51 IDLE,A,B,C,D: z <= 0 ;
52 E:z <= 1 ;
53 default :z <= 0 ;
54 endcase end
55 end
56 endmodule
57
2 input nrst,clk;
3 input x;
4 output z;
5 reg z;
6
7 reg [ 4 : 0 ]CS,NS;
8 parameter [ 4 : 0 ]
9 IDLE = 5 ' b00000,
10 A = 5 ' b00001,
11 B = 5 ' b00010,
12 C = 5 ' b00100,
13 D = 5 ' b01000,
14 E = 5 ' b10000;
15
16 always @( posedge clk or negedge nrst)
17 begin
18 if ( ! nrst)
19 CS <= IDLE;
20 else
21 CS <= NS;
22 end
23
24 always @(nrst or CS or x)
25 begin
26 NS = 5 ' bx;
27 case (CS)
28 IDLE: begin
29 if (x == 1 ) NS = A; else NS = IDLE; end
30 A: begin
31 if (x == 0 ) NS = B; else NS = A; end
32 B: begin
33 if (x == 0 ) NS = C; else NS = A; end
34 C: begin
35 if (x == 1 ) NS = D; else NS = IDLE; end
36 D: begin
37 if (x == 0 ) NS = E; else NS = A; end
38 E: begin
39 if (x == 0 ) NS = C; else NS = A; end
40 default :
41 NS = IDLE;
42 endcase
43 end
44
45 always @( posedge clk or negedge nrst)
46 begin
47 if ( ! nrst) z <= 1 ' b0;
48 else begin
49 z <= 1 ' b0;
50 case (NS)
51 IDLE,A,B,C,D: z <= 0 ;
52 E:z <= 1 ;
53 default :z <= 0 ;
54 endcase end
55 end
56 endmodule
57
做仿真时没有写testbench,直接用Quartus II 8.1里的仿真工具进行了功能仿真,波形如下:
试验结果表明改写三段式状态机成功。