verilog幂次方_verilog语法实例学习(3)

+，-，*，/，**(加/减/乘/除/幂运算)，乘法运算的结果的位宽是乘数和被乘数位宽的和。

在进行整数的除法运算时，结果要略去小数部分，只取整数部分；而进行取模运算时(%，亦称作求余运算符)结果的符号位采用模运算符中第一个操作数的符号。

-10%3 =-1 11%-3 结果为2

注意：在进行算术运算时，如果某一个操作数有不确定的值x，则整个结果也为不确定值x。下面的代码演示了算术运算符的操作，其结果为：

如果不指定reg signed类型，负数的运算会被当作无符号数运算，从而得到错误的结果。

Compiler version M-2017.03-SP2-11; Runtime version M-2017.03-SP2-11;  Dec 28 09:33 2018

32 +          15 =          47

32 -          15 =          17

15 -          32 =         -17

32 *          15 =         480

32 *         -32 =       -1024

32 /          15 =           2

-32 mod          15 =          -2

32 mod          -3 =           2

3 **           2 =           9

32 +         15 =         47

32 -         15 =         17

15 -         32 = 4294967279

32 *         15 =        480

32 * 4294967264 = 4294966272

32 /         15 =          2

4294967264 mod         15 =         14

32 mod 4294967293 =         32

3 **          2 =          9

V C S   S i m u l a t i o n   R e p o r t

`timescale 1ns/1ns

module operator;

reg signed [31:0] a = 32;

reg signed [31:0] b = 15;

reg signed [31:0] c = -32;

reg signed [31:0] d = -3;

reg signed [31:0] e = 3;

reg signed [31:0] f = 2;

reg signed [31:0] r = 1;

reg [31:0] a1 = 32;

reg [31:0] b1 = 15;

reg [31:0] c1 = -32;

reg [31:0] d1 = -3;

reg [31:0] e1 = 3;

reg [31:0] f1 = 2;

reg [31:0] r1 = 1;

initial begin

r = a + b;

$display("%d + %d = %d",a, b, r);

r = a - b;

$display("%d - %d =