寄存器模型
uvm_reg_sequence是UVM自带所有register sequence 的基类。 该类包含model, adapter, reg_seqr(uvm_sequencer). 感觉寄存器模型是个小的UVM系统。有自己uvm_reg_item, uvm_reg_sequence,reg_seqr, uvm_reg_adapter 是用来将寄存器的transaction 和 physical bus transaction之间的转化
//------------------------------------------------------------------------------ // TITLE: Register Sequence Classes //------------------------------------------------------------------------------ // // This section defines the base classes used for register stimulus generation. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // // CLASS: uvm_reg_sequence // // This class provides base functionality for both user-defined RegModel test // sequences and "register translation sequences". // // - When used as a base for user-defined RegModel test sequences, this class // provides convenience methods for reading and writing registers and // memories. Users implement the body() method to interact directly with // the RegModel model (held in the <model> pr