UVM Top Testbench

top testbench在top_tb中包含进所有的文件，将DUT放在top_tb中（例化DUT），连接好各个端口，提供clk时钟和rst_n复位信号。最主要的是要给组件中的虚接口设置接口，一般是给driver和monitor的虚接口例化接口。初始化run_test()使其自动启动UVM仿真。用config机制配置内部变量。如例：

 1 `timescale 1ns/1ps
 2 `include "uvm_macros.svh"
 3 
 4 import uvm_pkg::*;
 5 `include "my_if.sv"
 6 `include "my_transaction.sv"
 7 `include "my_sequencer.sv"
 8 `include "my_driver.sv"
 9 `include "my_monitor.sv"
10 `include "my_agent.sv"
11 `include "my_model.sv"
12 `include "my_scoreboard.sv"
13 `include "my_sequence.sv"
14 `include "my_env.sv"
15 `include "base_test.sv"
16 
17 module top_tb;
18 
19 reg clk;
20 reg rst_n;
21 reg[7:0] rxd;
22 reg rx_dv;
23 wire[7:0] txd;
24 wire tx_en;
25 
26 my_if input_if(clk, rst_n);
27 my_if output_if(clk, rst_n);
28 
29 dut my_dut(.clk(clk),
30            .rst_n(rst_n),
31            .rxd(input_if.data),
32            .rx_dv(input_if.valid),
33            .txd(output_if.data),
34            .tx_en(output_if.valid));
35 
36 initial begin
37    clk = 0;
38    forever begin
39       #100 clk = ~clk;
40    end
41 end
42 
43 initial begin
44    rst_n = 1'b0;
45    #1000;
46    rst_n = 1'b1;
47 end
48 
49 initial begin
50    run_test("base_test");
51 end
52 
53 initial begin
54    uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.drv", "vif", input_if);
55    uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.mon", "vif", input_if);
56    uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.o_agt.mon", "vif", output_if);
57 end
58 
59 endmodule

 

参考文献：

[1] 测试平台说明. http://www.asicdv.com/uvm_scan.asp?id=39.

[2] 张强. UVM实战. 机械工业出版社. 2014.07.

 

转载于:https://www.cnblogs.com/dpc525/p/5418622.html