uvm_primer ch18 put/get port的应用
用来拆分出sequence
virtual class base_tester extends uvm_component;
`uvm_component_utils(base_tester)
virtual tinyalu_bfm bfm;
uvm_put_port #(command_s) command_port;//重点
function void build_phase(uvm_phase phase);
command_port = new("command_port", this);
endfunction : build_phase
pure virtual function operation_t get_op();
pure virtual function byte get_data();
task run_phase(uvm_phase phase);
byte unsigned iA;
byte unsigned iB;
operation_t op_set;
command_s command;
phase.raise_objection(this);
command.op = rst_op;
command_port.put(command); //重点
repeat (1000) begin : random_loop
command.op = get_op();
command.A = get_data();
command.B = get_data();
command_port.put(command);
end : random_loop
#500;
phase.drop_objection(this);
endtask : run_phase
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new
endclass : base_tester
class driver extends uvm_component;
`uvm_component_utils(driver)
virtual tinyalu_bfm bfm;
uvm_get_port #(command_s) command_port; //重点
function void build_phase(uvm_phase phase);
if(!uvm_config_db #(virtual tinyalu_bfm)::get(null, "*","bfm", bfm))
$fatal("Failed to get BFM");
command_port = new("command_port",this);
endfunction : build_phase
task run_phase(uvm_phase phase);
command_s command;
shortint result;
forever begin : command_loop
command_port.get(command); //重点
bfm.send_op(command.A, command.B, command.op, result);
end : command_loop
endtask : run_phase
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new
endclass : driver
总是将export传入port的connect方法中;
driver 和sequencer连接
问题
driver侧,是线程间通信,
monitor侧是线程内通信, WHY???