SDAccel_Examples/getting_started/rtl_kernel/ ---- github
//top
///
// Description: This is a wrapper of module "krnl_vadd_rtl_int"
///
// default_nettype of none prevents implicit wire declaration.
`default_nettype none
`timescale 1 ns / 1 ps
module krnl_vadd_rtl #(
parameter integer C_S_AXI_CONTROL_DATA_WIDTH = 32,
parameter integer C_S_AXI_CONTROL_ADDR_WIDTH = 6,
parameter integer C_M_AXI_GMEM_ID_WIDTH = 1,
parameter integer C_M_AXI_GMEM_ADDR_WIDTH = 64,
parameter integer C_M_AXI_GMEM_DATA_WIDTH = 32
)
(
// System signals
input wire ap_clk,
input wire ap_rst_n,
// AXI4 master interface
output wire m_axi_gmem_AWVALID,
input wire m_axi_gmem_AWREADY,
output wire [C_M_AXI_GMEM_ADDR_WIDTH-1:0] m_axi_gmem_AWADDR,
output wire [C_M_AXI_GMEM_ID_WIDTH - 1:0] m_axi_gmem_AWID,
output wire [7:0] m_axi_gmem_AWLEN,
output wire [2:0] m_axi_gmem_AWSIZE,
// Tie-off AXI4 transaction options that are not being used.
output wire [1:0] m_axi_gmem_AWBURST,
output wire [1:0] m_axi_gmem_AWLOCK,
output wire [3:0] m_axi_gmem_AWCACHE,
output wire [2:0] m_axi_gmem_AWPROT,
output wire [3:0] m_axi_gmem_AWQOS,
output wire [3:0] m_axi_gmem_AWREGION,
output wire m_axi_gmem_WVALID,
input wire m_axi_gmem_WREADY,
output wire [C_M_AXI_GMEM_DATA_WIDTH-1:0] m_axi_gmem_WDATA