task my_model::main_phase(uvm_phase phase);
my_transaction tr;
my_transaction new_tr;
super.main_phase(phase);
logic signed [14:0] i; //变量定义不能再task中间 wrong
while<
uvm task 变量定义只能在开头
最新推荐文章于 2023-03-05 11:20:36 发布
task my_model::main_phase(uvm_phase phase);
my_transaction tr;
my_transaction new_tr;
super.main_phase(phase);
logic signed [14:0] i; //变量定义不能再task中间 wrong
while<