bug分析
task my_scoreboard::main_phase(uvm_phase phase);
my_transaction get_expect, get_actual, tmp_tran;
bit result;
//fortest begin--------
real a_r = -1.5; //1.5-->2 -1.5-->-2
real b_r = -1.4; //1.4-->1 -1.4-->-1
real c_r = -1.6; //1.6-->2 -1.6-->-2
logic signed [20:0] a21;
logic signed [14:0] a15;
`uvm_info(get_full_name