`timescale 1ns/1ps
module my_func
(
clk,
rd_reset_n,
rd_ptr_inc,
sync_wr_ptr
);
input clk;
input rd_reset_n;
input [1:0] rd_ptr_inc;
input [3:0] sync_wr_ptr;
parameter W = 35;
parameter DP = 2;
parameter WR_FAST = 1'b0;
parameter RD_FAST = 1'b1;
parameter AW=7;
wire [AW:0] rd_cnt = get_cnt(sync_wr_ptr, rd_ptr_inc);
reg [AW:0] grey_rd_ptr;
always @(posedge clk or negedge rd_reset_n) begin
if (!rd_reset_n) begin
grey_rd_ptr <= 0;
end
else begin
grey_rd_ptr <= bin2grey(rd_ptr_inc);
if (rd_cnt==1) begin
end
end
end
function [AW:0] bin2grey;
input [AW:0] bin;
reg [8:0] bin_8;
reg [8:0] grey_8;
begin
bin_8 = bin;
grey_8[1:0] = do_grey(bin_8[2:0]);
grey_8[3:2] = do_grey(bin_8[4:2]);
grey_8[5:4] = do_grey(bin_8[6:4]);
grey_8[7:6] = do_grey(bin_8[8:6]);
grey_8[8] = bin_8[8];
bin2grey = grey_8;
end
endfunction
function [AW:0] grey2bin;
input [AW:0] grey;
reg [8:0] grey_8;
reg [8:0] bin_8;
begin
grey_8 = grey;
bin_8[8] = grey_8[8];
bin_8[7:6] = do_bin({bin_8[8], grey_8[7:6]});
bin_8[5:4] = do_bin({bin_8[6], grey_8[5:4]});
bin_8[3:2] = do_bin({bin_8[4], grey_8[3:2]});
bin_8[1:0] = do_bin({bin_8[2], grey_8[1:0]});
grey2bin = bin_8;
end
endfunction
function [1:0] do_grey;
input [2:0] bin;
begin
if (bin[2]) begin
case (bin[1:0])
2'b00: do_grey = 2'b10;
2'b01: do_grey = 2'b11;
2'b10: do_grey = 2'b01;
2'b11: do_grey = 2'b00;
endcase
end
else begin
case (bin[1:0])
2'b00: do_grey = 2'b00;
2'b01: do_grey = 2'b01;
2'b10: do_grey = 2'b11;
2'b11: do_grey = 2'b10;
endcase
end
end
endfunction
function [1:0] do_bin;
input [2:0] grey;
begin
if (grey[2]) begin
case (grey[1:0])
2'b10: do_bin = 2'b00;
2'b11: do_bin = 2'b01;
2'b01: do_bin = 2'b10;
2'b00: do_bin = 2'b11;
endcase
end
else begin
case (grey[1:0])
2'b00: do_bin = 2'b00;
2'b01: do_bin = 2'b01;
2'b11: do_bin = 2'b10;
2'b10: do_bin = 2'b11;
endcase
end
end
endfunction
function [AW:0] get_cnt;
input [AW:0] wr_ptr, rd_ptr;
begin
if (wr_ptr >= rd_ptr) begin
get_cnt = (wr_ptr - rd_ptr);
end
else begin
get_cnt = DP*2 - (rd_ptr - wr_ptr);
end
end
endfunction
endmodule
`timescale 1ns/1ps
module tb_my_func();
parameter PERIOD=10;
reg [1:0] rd_prt_inc;
reg rd_reset_n;
reg clk;
reg [3:0] sync_wr_ptr ;
initial begin
clk=0;
forever clk = #(PERIOD/2) ~clk;
end
initial begin
rd_reset_n=0;
rd_prt_inc=0;
#10 rd_reset_n=1;
rd_prt_inc=2'b01;
sync_wr_ptr = 5;
#10 rd_prt_inc=2'b10;sync_wr_ptr = 8;
#10 rd_prt_inc=2'b00;sync_wr_ptr = 10;
#10 rd_prt_inc=2'b11;sync_wr_ptr = 13;
end
my_func uut(
.clk(clk),
.rd_reset_n(rd_reset_n),
.rd_ptr_inc(rd_prt_inc),
.sync_wr_ptr(sync_wr_ptr)
);
endmodule