【AIE】firD/Xilinx Versal - Insert AI Engine into your custom PL design and take it to hardware in 15m

斐非韭

已于 2024-01-28 18:00:17 修改

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分类专栏： FPGA 文章标签： fpga开发

于 2023-11-24 14:55:50 首次发布

本文链接：https://blog.csdn.net/weixin_39060517/article/details/134598702

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请添加图片描述

https://www.youtube.com/watch?v=18J8RRIbrAM

在这里插入图片描述

下图是通过connectivity 实现的，PLIO, 没有用HLS

在这里插入图片描述

//graph.cpp
#include "graph.h"

fir_filter uut;

int main(int argc, char ** argv)
{
	uut.init();
	uut.run();
	uut.end();
	return 0;
}
//------------------
#pragma once

#include <adf.h>
#include "fir_sr_sym_graph.hpp"

using namespace adf;

#define TT_DATA int16
#define TT_COEF int16
#define TP_FIR_LEN 33
#define TP_SHIFT 15
#define TP_RND 0
#define TP_INPUT_WINDOW_VSIZE 512

class fir_filter : public graph
{
	private:
		std::vector<TT_COEF> m_taps_v = std::vector<TT_COEF>{
			-12, -147, -153, -84, 121, 377, 505, 321,
			-220,-921, -1356, -1040, 304, 2537, 5076, 7089,
			7856
		};

		xf::dsp::aie::fir::sr_sym::fir_sr_sym_graph
		<
			TT_DATA,
			TT_COEF,
			TP_FIR_LEN,
			TP_SHIFT,
			TP_RND,
			TP_INPUT_WINDOW_VSIZE
		> fir_kernel;

	public:
		input_plio in;
		output_plio out;

		fir_filter() : fir_kernel(m_taps_v)
		{
			in = input_plio::create("DataIn1", plio_64_bits, "data/input.txt");
			out = output_plio::create("DataOut1", plio_64_bits, "data/output.txt");

			auto kernels = fir_kernel.getKernels();
			adf::runtime<adf::ratio>(kernels[0])=0.99;

			connect<>(in.out[0], fir_kernel.in[0]);
			connect<>(fir_kernel.out[0], out.in[0]);

		};

};

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/09/2023 07:21:02 AM
// Design Name: 
// Module Name: axis_adder
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module axis_adder(
    input aclk,
    input resetn,
    
    input s_axis1_tvalid,
    output s_axis1_tready,
    input signed [15:0] s_axis1_tdata,
    
    input s_axis2_tvalid,
    output s_axis2_tready,
    input signed [15:0] s_axis2_tdata,
    
    output m_axis_tvalid,
    input m_axis_tready,
    output signed [15:0] m_axis_tdata
    );
    
    
    
    assign m_axis_tvalid = s_axis1_tvalid && s_axis2_tvalid;
    assign s_axis1_tready = m_axis_tready;
    assign s_axis2_tready = m_axis_tready;
    assign m_axis_tdata = s_axis1_tdata + s_axis2_tdata;
endmodule