顶层模块
module top(
input clk,
input rst_n,
input key,
output beep
);
wire key_vlaue;
wire key_flag;
parameter Delay_time=20'd400_000;//20Mhz晶振,一个时钟周期50nm,延时20ms需要400_000个时钟周期
key_debounce #(
.Delay_time (Delay_time)
)u_key_debounce(
.clk (clk),
.rst_n (rst_n),
.key (key),
.key_value (key_vlaue),
.key_flag (key_flag)
);
beep_ctrl u_beep_ctrl(
.clk (clk),
.rst_n (rst_n),
.key_flag (key_flag),
.key_value (key_vlaue),
.beep (beep)
);
endmodule
消抖模块
module key_debounce(
input clk,
input rst_n,
input key,
output reg key_value,
output reg key_flag
);
reg key_reg;
reg [19:0] delay_cnt;
parameter Delay_time=20'd1000_000;//50Mhz晶振,一个时钟周期20nm,延时20ms需要1000_000个时钟周期
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
key_reg <= 1'b1;
delay_cnt <= 20'd0;
end
else begin
key_reg <= key;
if(key != key_reg)
delay_cnt <= Delay_time;
else begin
if(delay_cnt>20'd0)
delay_cnt <= delay_cnt - 1'b1;
else
delay_cnt <=20'd0;
end
end
end
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
key_value <= 1'b1;
key_flag <= 1'b0;
end
else begin
if(delay_cnt == 20'b1) begin
key_flag <= 1'b1;
key_value <= key;
end
else begin
key_flag <= 1'b0;
key_value <= key_value;
end
end
end
endmodule
控制输出模块
module beep_ctrl(
input clk,
input rst_n,
input key_flag,
input key_value,
output reg beep
);
always @ (posedge clk or negedge rst_n) begin
if(!rst_n)
beep <= 1'b1;
else
if(key_flag & (~key_value))
beep <= ~beep;
else
beep <= beep;
end
endmodule
测试仿真程序
module u_top;
// Inputs
reg clk;
reg rst_n;
reg key;
// Outputs
wire beep;
// Parameter
parameter Delay_time=20'd10; //20Mhz晶振,一个时钟周期50nm,延时500nm需要10个时钟周期
// Instantiate the Unit Under Test (UUT)
top #
(.Delay_time (Delay_time))
uut
( .clk(clk),
.rst_n(rst_n),
.key(key),
.beep(beep)
);
always #25 clk=~clk;
initial begin
// Initialize Inputs
clk = 0;
rst_n = 0;
key = 1;
// Wait 100 ns for global reset to finish
#25;
rst_n = 1;
#100;
key = 0;
#550;
key =1;
#100;
key = 0;
#25;
key = 1;
#25;
key = 0;
#525;
key = 1;
#100;
key = 0;
#25;
key = 1;
#25;
key = 0;
#600;
key = 1;
#800;
rst_n = 0;
// Add stimulus here
end
endmodule
仿真结果