电力电子转战数字IC20220521day5——半整数分频

3.5分频的解题思路：用上升沿和下降沿做两个7分频然后逻辑或

自己写出来的跑出来总是没有结果，暂时是没有结果，。

module threed5fd(clk,rst,clk3);
//3.5分频，用两个沿做两个7分频（奇数）后，逻辑或得到3.5分频。
input clk;
input rst;
output clk3;
reg [2:0] count1;
reg [2:0] count2;
reg clk1,clk2,clk3r;
assign clk3=clk3r;

always @(posedge clk or negedge rst)
	if(!rst)
		 count1<=3'd0;  
		else if(count1==3'd0 || count1==3'd1)
			begin clk1<=!clk1; count1<=count1+3'd1; end
				else if(count1==3'd6)
				count1<=3'd0; 
					else count1<=count1+3'd1;
			
always @(negedge clk or negedge rst)
	if(!rst)
		 count2<=3'd0; 
		else if(count2==3'd3 || count2==3'd4)
			begin clk2<=!clk2; count2<=count2+3'd1; end
				else if(count2==3'd6)
				count2<=3'd0;	
				else count2<=count2+3'd1;
				
always clk3r=clk1 ||clk2;

endmodule

最后还是用文章中的代码尝试出来了，三个clk都是wire型，新的条件语句assign wire= 语句1？是则执行：否则执行；

//module threed5fd(clk,rst,clk3);
//input clk;
//input rst;
//output clk3;
//reg [2:0] count1;
//reg [2:0] count2;
//reg clk1,clk2,clk3r;
//assign clk3=clk3r;
//
//always @(posedge clk or negedge rst)
//	if(!rst)
//		 count1<=3'd0;  
//		else if(count1==3'd0 || count1==3'd1)
//			begin clk1<=!clk1; count1<=count1+3'd1; end
//				else if(count1==3'd6)
//				count1<=3'd0; 
//					else count1<=count1+3'd1;
//			
//always @(negedge clk or negedge rst)
//	if(!rst)
//		 count2<=3'd0; 
//		else if(count2==3'd3 || count2==3'd4)
//			begin clk2<=!clk2; count2<=count2+3'd1; end
//				else if(count2==3'd6)
//				count2<=3'd0;	
//				else count2<=count2+3'd1;
//				
//always clk3r=clk1 ||clk2;

endmodule

tb

`timescale 1ps/1ps

module threed5fdtest;
reg clk,rst;
wire clk3;

threed5fd t1(.clk(clk), .rst(rst), .clk3(clk3));

always #5 clk=~clk;

always
	begin
	clk=0;rst=1;
	#10 rst=0;
	#15 rst=1;
	#90 rst=0;
	#110 rst=1;
	#200 $stop;
	end

endmodule