电力电子转战数字IC20220715day49——UVM的phase机制

目录

6. phase机制

UVM编译和运行的顺序

uvm_top的职责

UVM仿真结束

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6. phase机制

• SV不能做到的：虽然通过new函数例化对象，在验证env实现层次化时无法保证例化的先后关系，以及各个组件在例化后的连接；顶层到底层的配置时无法在底层组件例化之前完成对底层的配置逻辑
• 作用：将uvm仿真阶段层次化，有先后。不仅是各个phase的先后执行顺序，同一phase中的层次化组件之间的phase也有先后关系
• 9个phase对应9个方法，只有component具备这9个，主要用build，connect，run，report。运行顺序自上到下

class subcomp extends uvm_component;
`uvm_component_utils (subcomp)
function new (string name, uvm_component parent);
	super.new(name, parent);
endfunction

function void build_phase (uvm_phase phase);//传递当前的phase进来
	`uvm_info("build_phase", "", UVM_LOW)
endfunction

function void connect_phase (uvm_phase phase);
	`uvm_info("connect_phase", "", UVM_LOW)
endfunction

function void end_of_elaboration_phase (uvm_phase phase);
	`uvm_info("end_of_elaboration_phase", "", UVM_LOW)
endfunction

function void start_of_elaboration_phase (uvm_phase phase);
	`uvm_info("start_of_elaboration_phase", "", UVM_LOW)
endfunction

task run_phase (uvm_phase phase);
	`uvm