verilog时钟翻转怎么写_数字时钟(verilog程序)

秒模块

module second (clk1,rst,s,enmin);

input clk1,rst;

output[6:0]s;

output enmin;

reg [6:0]s;

reg enmin;

always@(posedge clk1 or negedge rst)

begin if(!rst) begin s[6:0]&lt=7'h0;enmin&lt=0;end

else

begin if(s[6:0]&lt=59)

begin enmin&lt=1;s[6:0]&lt=0;end

else if(s[3:0]&lt=9)

begin s[6:4]=s[6:4]+1;s[3:0]&lt=0;enmin&lt=0;end

else begin s[6:4]&lt=s[6:4];s[3:0]&lt=s[3:0]+1;enmin&lt=0;end

end end

endmodule

分模块

module min(clk1,rst,m,enh);

input clk1,rst;

output[6:0]m;

output enh;

reg [6:0]m;

reg enh;

always@(posedge clk1 or negedge rst)

begin if(!rst) begin m[6:0]&lt=7'h0;enh&lt=0;end

else

begin if(m[6:0]&lt=59)

begin enh&lt=1;m[6:0]&lt=0;end

else if(m[3:0]&lt=9)

begin m[6:4]=m[6:4]+1;m[3:0]&lt=0;enh&lt=0;end

else begin m[6:4]&lt=m[6:4];m[3:0]&lt=m[3:0]+1;enh&lt=0;end

end end

endmodule

时模块

module hour(clk1,rst,h);

input clk1,rst;

output[6:0]h;

reg [5:0]h;

reg [6:0]s,m;

always@(posedge clk1 or negedge rst)

begin if(!rst)

begin h[5:0]&lt=5'h0;end

else

begin if(h[5:0]==5'h23&m[6:0]==7'h59&s[6:0]==7'h59)

begin h[5:0]&lt=6'h0;m[6:0]&lt=7'h0;s[6:0]&lt=7'h0;end

else

if(h[3:0]==4'h9)

begin h[3:0]&lt=4'h0;h[5:4]&lt=h[5:4]+1;end

else

begin h[3:0]&lt=h[3:0]+1;h[5:4]&lt=h[5:4];end

end end

endmodule

scand_led模块

module scan_led(clk,rst,s,m,h,dig,seg);

input clk,rst;

input[6:0]s,m;

input [5:0]h;

output dig,seg;

reg[7:0]dig,seg;

reg[2:0]count; reg[3:0]num;

always@(posedge clk or negedge rst)

begin if(!rst) count&lt=0;

else count&lt=count+1;

end

always@(count)

begin case(count)

0:begin dig=8'b11111110;num&lt=s[3:0];end

1:begin dig=8'b11111101;num&lt=s[6:4];end

2:begin dig=8'b11111011;num&lt=4'ha;end

3:begin dig=8'b11110111;num&lt=m[3:0];end

4:begin dig=8'b11101111;num&lt=m[6:4];end

5:begin dig=8'b11011111;num&lt=4'ha;end

6:begin dig=8'b10111111;num&lt=h[3:0];end

7:begin dig=8'b01111111;num&lt=h[5:4];end

default:dig=8'b11111111;

endcase

end

always@(num)

begin case(num)

4'h0:seg = 8'hc0;

4'h1:seg = 8'hf9;

4'h2:seg = 8'ha4;

4'h3:seg = 8'hb0;

4'h4:seg = 8'h99;

4'h5:seg = 8'h92;

4'h6:seg = 8'h82;

4'h7:seg = 8'hf8;

4'h8:seg = 8'h80;

4'h9:seg = 8'h90;

4'ha:seg = 8'hbf;

default:seg = 8'hc0;

endcase

end

endmodule

speak模块

module speaker(clk2,rst,m,s,speak);

input clk2,rst; input [6:0]m,s;

output speak;

assign speak=((m[6:0]==7'h0&s[6:0]&lt10)?clk2:0);

endmodule