module clock(clk,out,reset,cin,ocom,count,countmin,tgm,tdm,tgs,tds);
output[3:0] ocom;
output[7:0] out;
output count,countmin;
input cin,clk,reset;
input tgm;
//
高位的分
input tdm;
//
地位的分
input tgs;
//
高位的秒
input tds;
//
地位的秒
reg [7:0] out_s;
reg[7:0] out_min;
reg[7:0] out;
reg[3:0] ocom;
reg[3:0] in_out;
reg clk_m,clk_n;
reg[1:0] select;
reg count;
reg countmin;
integer count_clk,count_cp;
always @(posedge clk)
if (count_cp == 50000)
//50MHZ
做
50000
次分频,取反后得到
2ms
的时间
begin
count_cp = 0;
clk_n = ~clk_n;
end
else
count_cp = count_cp + 1;
always @(posedge