module UsignedToSigned(
input wire clk,
input wire rst,
input wire data_in_en,
input wire [11:0] data0_in,
input wire [11:0] data1_in,
input wire [11:0] data2_in,
input wire [11:0] data3_in,
output reg data_out_en,
output reg [11:0] data0_out,
output reg [11:0] data1_out,
output reg [11:0] data2_out,
output reg [11:0] data3_out
);
always @(posedge clk or negedge rst)begin
if(rst)begin
data_out_en <= 0;
end
else if(data_in_en == 1'b1)begin
data_out_en <= 1'b1;
end
else begin
data_out_en <= 0;
end
end
always @(posedge clk or negedge rst)begin
if (rst)begin
data0_out <= 0;
data1_out <= 0;
data2_out <= 0;
data3_out <= 0;
end
else if(data_in_en == 1'b1) begin
data0_out <= $signed(data0_in);
data1_out <= $signed(data1_in);
data2_out <= $signed(data2_in);
data3_out <= $signed(data3_in);
end
else begin
data0_out <= 0;
data1_out <= 0;
data2_out <= 0;
data3_out <= 0;
end
end
endmodule
05-19
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08-26
854
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