tb仿真文件

module tb_DDC_fir_D40();
    reg clk_tb;
    reg rst_tb;
    reg data_in_en_tb;    
    reg [11:0] data0_in_tb;
    reg [11:0] data1_in_tb;
    reg [11:0] data2_in_tb;
    reg [11:0] data3_in_tb;
    
    wire data_out_en_tb;            
    wire signed [15:0] data_out_I_tb;
    wire signed [15:0] data_out_Q_tb;

    reg signed [15:0] memory_0 [1279:0] ;
    reg signed [15:0] memory_1 [1279:0] ;
    reg signed [15:0] memory_2 [1279:0] ;
    reg signed [15:0] memory_3 [1279:0] ;
    
/
    parameter PERIOD = 8;   
    initial begin   
     clk_tb = 1'b1;   
     forever    
     #(PERIOD/2) clk_tb = ~clk_tb;    
    end  

initial begin
    rst_tb = 1'b1;
    #160;
    rst_tb = 1'b0;
    #80;         
    

    $readmemh("C:/Users/wanbowen.DOMAIN_XF/Desktop/initiative_signal_processing/DDC_fir_D40/DDC_fir_D40.srcs/sim_1/1.txt",memory_0); //读取数据到memory
    $readmemh("C:/Users/wanbowen.DOMAIN_XF/Desktop/initiative_signal_processing/DDC_fir_D40/DDC_fir_D40.srcs/sim_1/2.txt",memory_1);
    $readmemh("C:/Users/wanbowen.DOMAIN_XF/Desktop/initiative_signal_processing/DDC_fir_D40/DDC_fir_D40.srcs/sim_1/3.txt",memory_2);
    $readmemh("C:/Users/wanbowen.DOMAIN_XF/Desktop/initiative_signal_processing/DDC_fir_D40/DDC_fir_D40.srcs/sim_1/4.txt",memory_3);
    
    data_in_en_tb = 1'b1;
//    repeat(1) begin
        filter_data;
//    end
    
    data_in_en_tb = 1'b0;
end    
///
    integer n;
    task filter_data;
        begin 
            for(n=0;n<1280;n=n+1) begin//把存储单元的数字读取
                data0_in_tb = memory_0[n];
                data1_in_tb = memory_1[n];
                data2_in_tb = memory_2[n];
                data3_in_tb = memory_3[n];
                #8;
                end 
        end
    endtask 
    
DDC_fir_D40 tb_DDC_fir_D40(
    .clk            (clk_tb        ) ,            
    .rst            (rst_tb        ) ,            
    .data_in_en     (data_in_en_tb ) ,            
    .data0_in       (data0_in_tb   ) ,    
    .data1_in       (data1_in_tb   ) ,     
    .data2_in       (data2_in_tb   ) ,    
    .data3_in       (data3_in_tb   ) ,    
               
    .data_out_en_ex (data_out_en_tb ) ,          
    .data_out_I_ex  (data_out_I_tb  ) ,
    .data_out_Q_ex  (data_out_Q_tb  )
);    
    

endmodule