FPGA
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How to optimize Priority encoder in FPGA
optimize a priority Mux encoder from 12 logic levels to 5原创 2022-06-09 06:13:09 · 112 阅读 · 0 评论 -
Some SystemVerliog functions
package global_functions_pkg;function int log2ceil(input int unsigned a); int i; int unsigned p2i; //int unsigned p2i = 1; begin p2i = 1; //for(i=0, p2i=1; p2i<a; i++) for(i=0; p2i<a; i++) p2i<&l.原创 2022-04-14 08:17:52 · 130 阅读 · 0 评论 -
FPGA TIMING CONSTRIANT(.sdc)
WHY WE NEED TIMING CONSTRAINT:RELAX TIMING REQUIREMENTSNomally set on "not real critical path"Some logic paths needmore than 1 cycle to propogate to next squential cellDefinitionsetup time:the amount of time the data at the synchronous input (...原创 2021-06-05 01:23:45 · 1066 阅读 · 0 评论 -
vivado,从rtl到bitstream以及如何用JTAG进行硬件测试
There are three stages in vivado from RTL to Bitstream(从逻辑设计到bitstream的三个阶段)综合: 这个步骤将会把你的硬件语言代码转换成netlist。In Synthesizeprocess, RTL design (verilog/VHDL) is compiled and translated into netlist implementation:这个步骤会把你生成的netlist投射到你选择型号的FPGA上, 并且能生成电路时间报.原创 2020-09-17 03:07:34 · 2036 阅读 · 1 评论 -
Quartus Signal Tap II Debugging
working environment:LinuxStepsOpen RTL project:open quartus under Linux:quartusopen project file (file that ends with .qpt)Signal tap IITool -> singal Tap IIAdding clocksignal configuration -> name:clock -> filter: Signal Tap II Pre-sy原创 2020-07-22 03:06:40 · 178 阅读 · 0 评论 -
Vivado block design with both AXI GPIO and custom IP (ZEDBOARD)
Custom IP: First step: Create a block design ->Tools -> Create and Package New IP -> Create new AXI4 Peripheral -> set a name for your new IP.(This IP will be saved under a file named "ip_...原创 2018-07-06 12:45:41 · 991 阅读 · 0 评论 -
Use EMIO and MIO to control Pmod GPIOS on zedboard by vivado and SDK (Zedboard)
AXI GPIOs can be set to either read or write:Step one, create block design in vivado:原创 2018-07-06 15:31:53 · 614 阅读 · 0 评论 -
FPGA vs ASIC
ASIC(Application Specific Integrated Circuit) is atype of IC that is designed with a certain purpose, the functionof ASIC is fixed after production.Advantages:High performance, high speed, low p...原创 2018-07-20 06:18:30 · 731 阅读 · 0 评论 -
Asynchronous FIFO with gray code(异步FIFO verilog设计理念)
代码来自asic world 和paper“ Simulation and Synthesis Techniques for Asynchronous FIFO Design”,文章解说均为自己的理解,如果有错误欢迎纠正~What is FIFO?FIFO 是一个满足“先进先出”的储存数据的结构,如果我以“A->B->C”的顺序存入数据,由于我先存入的C,那么我先读取的内...原创 2018-09-23 10:54:09 · 8791 阅读 · 0 评论