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Verilog
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How to optimize Priority encoder in FPGA
optimize a priority Mux encoder from 12 logic levels to 5原创 2022-06-09 06:13:09 · 116 阅读 · 0 评论 -
vivado,从rtl到bitstream以及如何用JTAG进行硬件测试
There are three stages in vivado from RTL to Bitstream(从逻辑设计到bitstream的三个阶段)综合: 这个步骤将会把你的硬件语言代码转换成netlist。In Synthesizeprocess, RTL design (verilog/VHDL) is compiled and translated into netlist implementation:这个步骤会把你生成的netlist投射到你选择型号的FPGA上, 并且能生成电路时间报.原创 2020-09-17 03:07:34 · 2070 阅读 · 1 评论 -
Verilog practice
Q1: write Verilog code to generate below waveform: Q2: write Verilog code to generate below waveform:Since there is one delay after the rising edge of data in, three delays after the negedge...原创 2018-07-07 08:51:04 · 328 阅读 · 0 评论 -
Asynchronous FIFO with gray code(异步FIFO verilog设计理念)
代码来自asic world 和paper“ Simulation and Synthesis Techniques for Asynchronous FIFO Design”,文章解说均为自己的理解,如果有错误欢迎纠正~What is FIFO?FIFO 是一个满足“先进先出”的储存数据的结构,如果我以“A->B->C”的顺序存入数据,由于我先存入的C,那么我先读取的内...原创 2018-09-23 10:54:09 · 8872 阅读 · 0 评论 -
Clock divider
1. Odd integer division(not 50% duty cycle)Design Moore machine (take "7" as example)2. Odd integer division with 50% duty cycleConceptually, the easiest way to create an odd divider with a 50...转载 2018-07-28 10:06:17 · 2678 阅读 · 0 评论 -
Use FSMD to interpret high level c++ code (用带有数据通道的有限状态机来编写c++方程)
Finite state machine with data path:FSMD has two parts, FSM and Datapath. It's a more flexible mechanism to control data in different stage than FSM. In a standard FSMA, FSM is used to change the st...原创 2019-03-19 04:13:38 · 289 阅读 · 0 评论 -
Using genvar to build delay block(Verilog genvar的使用)
Genvar is widly use when we want to instantiate lots of gates/modules. In this case, we use “genvar” to generate a delay block that usesregisters in serial.module delay(q,d,clock);output [WIDTH-1...原创 2019-05-08 03:00:11 · 409 阅读 · 0 评论