SytemVerilog
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Some SystemVerliog functions
package global_functions_pkg; function int log2ceil(input int unsigned a); int i; int unsigned p2i; //int unsigned p2i = 1; begin p2i = 1; //for(i=0, p2i=1; p2i<a; i++) for(i=0; p2i<a; i++) p2i<&l.原创 2022-04-14 08:17:52 · 136 阅读 · 0 评论 -
SystemVerilog note(2)
SV - OOP Concepts (object-oriented programming) Reference: http://www.verificationguide.com/p/systemverilog-classes_23.html class A class is a description of some group of things that have somethi...转载 2018-07-17 13:11:37 · 181 阅读 · 0 评论 -
SystemVerilog note (3)
SystemVerilog TestBench Example - ADDER Part 1 Transaction Fields required to generate the stimulus are declared in the transaction class. Transaction class can also be used as the placeholder ...转载 2018-07-19 12:51:00 · 279 阅读 · 0 评论 -
SytemVerilog note (1)
-----------------------Occasional Updates----------------------- I want to share some notes about SystemVerilog, I'm a beginner at this. Part1 Data Type: bit : unsigned; byte: signed. Part2 Task...转载 2018-07-07 00:58:21 · 233 阅读 · 0 评论