1.题目
2.源码
// *********************************************************************************
// Project Name : LED_Control
// Email : 2972880695@qq.com
// Website : https://home.cnblogs.com/u/hqz68/
// Create Time : 2019/12/13
// File Name : LED_Control.v
// Module Name : LED_Control
// Abstract :
// editor : sublime text 3
// *********************************************************************************
// Modification History:
// Date By Version Change Description
// -----------------------------------------------------------------------
// 2019/12/13 宏强子 1.0 Original
//
// *********************************************************************************
`timescale 1ns/1ns
module LED_Control (
//system signals
input sclk ,
input s_rst_n ,
//output
output led_r ,
output led_g ,
output led_y
);
//========================================================================\
// =========== Define Parameter and Internal signals ===========
//========================================================================/
//localparam time_1s = 10_000_000; //真实1s数字
localparam time_1s = 10_000; //加快仿真使用
reg [23:0] time_cnt ;
reg time_cnt_end ;
reg [2:0] num_cnt ;
reg [2:0] led ;
//=============================================================================
//**************************** Main Code *******************************
//=============================================================================
//一秒计数器
always @ (posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
time_cnt <= 24'd0;
else if (time_cnt <= time_1s -1)
time_cnt <= time_cnt + 1'b1;
else
time_cnt <= 24'd0;
end
//一秒标志
always @ (posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
time_cnt_end <= 1'b0;
else if (time_cnt == time_1s -2)
time_cnt_end <= 1'b1;
else
time_cnt_end <= 1'b0;
end
//次数计数器
always @ (posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
num_cnt <= 3'd0;
else if (num_cnt == 3'd6)
num_cnt <= 3'd0;
else if (time_cnt_end == 1'b1)
num_cnt <= num_cnt + 1'b1;
else
num_cnt <= num_cnt;
end
//时间段控制
always @ (posedge sclk or negedge s_rst_n) begin
if(s_rst_n == 1'b0)
led <= 3'd0;
else if (num_cnt <= 3'd1)
led <= 3'b100;
else if (num_cnt >= 3'd2 & num_cnt <= 3'd4)
led <= 3'b010;
else if (num_cnt >= 3'd5)
led <= 3'b001;
else
led <= 3'd0;
end
assign led_r = led[2];
assign led_g = led[1];
assign led_y = led[0];
endmodule
3.测试平台
`timescale 1ns/1ns
module tb_sim();
reg sclk ;
reg s_rst_n ;
wire led_r ;
wire led_g ;
wire led_y ;
initial begin
sclk = 1;
s_rst_n = 0;
#100
s_rst_n = 1;
end
always #50 sclk = ~sclk;
LED_Control LED_Control_inst(
//system signals
.sclk (sclk ),
.s_rst_n (s_rst_n ),
//output
.led_r (led_r ),
.led_g (led_g ),
.led_y (led_y )
);
endmodule
4.仿真波形