hdlbits-circuits-combinational logic-multiplexer

Mux256to1

Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.

Expected solution length: Around 1 line.

Module Declaration

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );

Hint...

• With this many options, a case statement isn't so useful.
• Vector indices can be variable, as long as the synthesizer can figure out that the width of the bits being selected is constant. In particular, selecting one bit out of a vector using a variable index will work.

my solution：

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
    assign out = in[sel];
endmodule

网页答案：

module top_module (
	input [255:0] in,
	input [7:0] sel,
	output  out
);

	// Select one bit from vector in[]. The bit being selected can be variable.
	assign out = in[sel];
	
endmodule

Mux256to1v

Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.

Expected solution length: Around 1–5 lines.

Module Declaration

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );

Hint...

• With this many options, a case statement isn't so useful.
• Vector indices can be variable, as long as the synthesizer can figure out that the width of the bits being selected is constant. It's not always good at this. An error saying "... is not a constant" means it couldn't prove that the select width is constant. In particular, in[ sel*4+3 : sel*4 ] does not work.
• Bit slicing ("Indexed vector part select", since Verilog-2001) has an even more compact syntax.

别人的答案（参考链接）：HDLBits 练习 Mux256to1v_assign out = in[sel*4+3-:4]-CSDN博客

1：

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    assign out = {in[sel*4+3],in[sel*4+2],in[sel*4+1],in[sel*4]};
endmodule

注意：不能写成assign out = in[sel*4+3:sel*4];

2：

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    assign out = in[sel*4+:4];
endmodule

这个表示 从 sel*4 开始，选择比特序号大于sel*4 的 4 位比特，相当于[sel4+3:sel*4]；

3：

assign out = in[sel*4+3-:4];

这个表示 从 sel*4+3 开始，选择比特序号小于 sel*4+3 的 4 位比特，相当于[sel*4+3:sel*4]；