利用Synopsys VCS对Verilog代码加密的方法
本人采用的VCS版本是2014版本,其他版本只提供参考;
方法一:
官方说明:
+autoprotect[ < file_suffix> ]
Creates a protected source file ; all modules are encrypted.
个人解释:
程序测试:
module Count(
input wire Sys_clk,
input wire Reset_n,
input wire count_en,
input wire count_clr,
output reg [4:0] count
);
always @(posedge Sys_clk or negedge Reset_n)
begin
if(~Reset_n)
count[4:0] <= 5'h0;
else if(count_clr)
count[4:0] <= 5'h0;
else if(count_en)
count[4:0] <= count[4:0]+1'b1;
else
count[4:0] <= count[4:0];
end
endmodule
module Count
`protected
g7FQH7O7G.&0[3CTc,^6_C&E-=P4IE:E7gS9S@Nf6eW-,cMWPP053)[Ndd^DE3:F
#JJd+AE36UgIBa8?f8LT2fG6+UNX9L&H?#-bP>;N7U(T[cOgQ;I_Ke[cF;=J]9\<
c(J0@CO?_5J#9b_Q1DEe=\4]9[bA.OeK1A6T+MREYH\.9e>9P?&6Pb>_Z6UL>E&L
WROQR941>dA/?E:EP.X[-b[#0JQb+];;Z.S=5#>80E(\H50PQKbHHfUYI&H=M_SB
=ISf_)d9-6-PA]RM4<6LW/A91Z)BVf?Wa[f.?[Ve&QRO?XD\3IJ1bAC/N=N_1EeK
UW3cUE/QDOaQ:B^@9_?.8VdB&>#FCcS7S+&R<2LL,-6fVd4)S_\abee:\S)+N/
=Y/XQ[/KM,Q]R5[J=H?cZRaT_RdIDX5-d&)Za&TbW(aK8/aRO(9ND-JGU.<HSPW,
B.-.HJL>?d]IED_P+QT>X<7U[@Mg(df^a2,b5PLZDRG-UJJ/\)g,6\Sd[>3H56\0
X>2B,d)0dJQLLU/K@)69IYDeEWEJ4^D3OZ,VUVE(\B+BF8211;/b6SSdM$
`endprotected
endmodule
方法二:
官方说明:
+auto2protect[ < file_suffix> ]
Create a protected source file that does not encrypt the port connection list
in the module header; all modules are encrypted.
个人解释:
对Verilog module内,除模块端口列表的所有内容加密;
程序测试:
module Count(
input wire Sys_clk,
input wire Reset_n,
input wire count_en,
input wire count_clr,
output reg [4:0] count
);
always @(posedge Sys_clk or negedge Reset_n)
begin
if(~Reset_n)
count[4:0] <= 5'h0;
else if(count_clr)
count[4:0] <= 5'h0;
else if(count_en)
count[4:0] <= count[4:0]+1'b1;
else
count[4:0] <= count[4:0];
end
endmodule
module Count(
input wire Sys_clk,
input wire Reset_n,
input wire count_en,
input wire count_clr,
output reg [4:0] count
);
`protected
.,1]W(LA?@Z\J9B4L.aP/e>T-HT-[GR70GU_IX<Jf/(JWDf>B:WW6)^N6<dGSba]
HeaTS\g14Ob.(>;NYdU2UcQ(+AN+SDcQe1OOI6E+6/Ye;/.L_bSR;M+?4AT0TI[Y
U[e1T.S#3UVM5\HX/8S763Ed26AQL@g6H#+B:EQ,-<[KQHcUXC;<8[:+E\TO.R1V
OK:.S+]CJaD9g^Dd[FB:.gS=UgNOLK#4G7^c=&Ma<(=RC4_YS:gHVD3=9Hg=YS4?
;-E/=PIJ\#A[ZAfP8OXJ56J-?]@QF;CWPGg1dDWI;I9^D@I&f)7-.FA9LcU7_+d)
>67bH.14EJG4NaQ>:FVfPbTIUV>M>D6VV;?XT#@6VEJ^5W[A32#GGQN,4C&4;8gg
WdJBQHXC-&]4*$
`endprotected
endmodule
方法三:
官方说明:
+auto3protect[ < file_suffix> ]
Creates a protected source file that does not encrypt the port connection list
in the module header or any parameter declarations that precede the first port
declaration; all modules are encrypted.
个人解释:
对Verilog module内,除模块端口列表、在端口列表前的参数声明以外的所有内容加密;
程序测试:
parameter m = 10;
module Count(
input wire Sys_clk,
input wire Reset_n,
input wire count_en,
input wire count_clr,
output reg [4:0] count
);
parameter n = 10;
always @(posedge Sys_clk or negedge Reset_n)
begin
if(~Reset_n)
count[4:0] <= 5'h0;
else if(count_clr)
count[4:0] <= 5'h0;
else if(count_en)
count[4:0] <= count[4:0]+1'b1;
else
count[4:0] <= count[4:0];
end
endmodule
parameter m = 10;
module Count(
input wire Sys_clk,
input wire Reset_n,
input wire count_en,
input wire count_clr,
output reg [4:0] count
);
`protected
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:T9O;MMN:(9f[PF>]+\F<X\QAWGBZ]B:g)T.fJFCeB:+->;N(?4:30NXG0UT8+QB
bV?WL[UPa01STAZCd:?24AJREL6+P?80>ZOV6Y,;;YA=DA(I=aJdAB@WdbXBUVDT
;KQ:C?IQPS[R/C+ID0@5;QJ-cZR2-X.4G8:(\6Ea]b^\>0&<faVb&c&^cB;\10<Z
9V=7]V0&<QOUf^SU[D-S]CSGf77Z)DAI9/=UISH8@S;SM;f+:dZe&(63>59]7HfD
4R4Ab7+CKSgP7,#<]X<XI>K?GWaDU3(D+[H0-Pg4HY2CQAfT<ASf01]J+aYCW;^Y
ZId+eLAG]dF?8JMT@FIPg):<5.,J@a+QZ.D_B@ZWdE[CA$
`endprotected
endmodule
方法四:
官方说明:
+protect[ < file_suffix> ]
Creates a protected source file ; only encrypting ` protect/` endprotect
regions.
个人解释:
对Verilog module内,`protect/endprotect的区域内进行加密;
程序测试:
module Count(
input wire Sys_clk,
input wire Reset_n,
input wire count_en,
input wire count_clr,
output reg [4:0] count
);
always @(posedge Sys_clk or negedge Reset_n)
begin
`protect
if(~Reset_n)
count[4:0] <= 5'h0;
else if(count_clr)
count[4:0] <= 5'h0;
`endprotect
else if(count_en)
count[4:0] <= count[4:0]+1'b1;
else
count[4:0] <= count[4:0];
end
endmodule
module Count(
input wire Sys_clk,
input wire Reset_n,
input wire count_en,
input wire count_clr,
output reg [4:0] count
);
always @(posedge Sys_clk or negedge Reset_n)
begin
`protected
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0ZJ[R7YETXYN:E8eOZ,MZHV7SH3WWNcH1b+J(ZV6T_1-/VA:;>BYC4a^b7eI:4BE
B=BR4UUT6Y^Q;WLM/eG-^+M98P03+NaOXH6bA1R@8ODefN,\dEQgcMa^O$
`endprotected
else if(count_en)
count[4:0] <= count[4:0]+1'b1;
else
count[4:0] <= count[4:0];
end
endmodule