FPGA高速采集系统

1.高速采集系统的功能和组成

2.高速ADC接口在FPGA中的实现

2.1总体设计

2.2 高速ADC的SPI接口

2.3高速ADC数据接收接口

下面所有用到的时钟，都是从AD_clk分频出来的同源时钟。

使用idelay做延时：


ug949

3数字下变频模块DDC实现的功能

3.1

3.2下变频模块的实现

3.3 下变频模块设计与仿真

3.4多相滤波器

半带滤波器：滤波器系数偶数位置为0，但是最中间那个系数不为0
这里设置通带为200M,采样率为1200M,那末整个带宽就为[-200M,200M],共400M带宽。
带通滤波器适合过滤，下采样后有镜像对称频谱的

滤波后：

3.5

一个数据对应一个valid信号

system generater

4三倍抽取

写.dat文件

close all;
clc ;
clear all;
%%parameters
SIMIIME=5000;           %simulation length
fs = 1200e6;            %sample frequency

%%产生单点频信号
L=4000;
f0=40e6;                %signnal frequency
t=0/fs:1/fs:(L-1)/fs;   %time granularrity
sig=exp(1j*(2*pi*f0*t));

%%
sig=awgn(sig,60);%将白高斯噪声添加到向量信号x中。标量snr指定了每一个采样点信号与噪声的比率，单位为dB。如果x是复数的，awgn将会添加复数噪声。这个语法假设x的能量是0dBW。
sig=sig/max(abs(sig));%归一化
sig=round(sig*(2^15-1));%将数据取成16bit
Len1=round(length(sig)/4);

din_i0(1:Len1)=round(real(sig(1:4:end)));
din_i1(1:Len1)=round(real(sig(2:4:end)));
din_i2(1:Len1)=round(real(sig(3:4:end)));
din_i3(1:Len1)=round(real(sig(4:4:end)));

din_q0(1:Len1)=round(imag(sig(1:4:end)));
din_q1(1:Len1)=round(imag(sig(2:4:end)));
din_q2(1:Len1)=round(imag(sig(3:4:end)));
din_q3(1:Len1)=round(imag(sig(4:4:end)));

len_t=length(din_i0);
sig_reg_i=zeros(1,len_t*4);
sig_reg_q=zeros(1,len_t*4);

sig_reg_i(1:4:end)=din_i0;
sig_reg_i(2:4:end)=din_i1;
sig_reg_i(3:4:end)=din_i2;
sig_reg_i(4:4:end)=din_i3;

sig_reg_q(1:4:end)=din_q0;
sig_reg_q(2:4:end)=din_q1;
sig_reg_q(3:4:end)=din_q2;
sig_reg_q(4:4:end)=din_q3;

sig_reg = complex(sig_reg_i,sig_reg_q);
freqz(sig_reg,fs);

%% write data
file1='din_i0.dat';
fp=fopen(file1,'w');
for loop=1:length(din_i0)
    if din_i0(loop)>=0
        din_i00=dec2bin(din_i0(loop),16);
    else
        din_i01=dec2bin(bitxor(abs(din_i0(loop)),2^16-1)+1);%
        din_i00=din_i01(end-15:end);
    end
    fprintf(fp,'%s\n',din_i00);
end
fclose(fp);

file1='din_i1.dat';
fp=fopen(file1,'w');
for loop=1:length(din_i1)
    if din_i1(loop)>=0
        din_i00=dec2bin(din_i1(loop),16);
    else
        din_i01=dec2bin(bitxor(abs(din_i1(loop)),2^16-1)+1);%
        din_i00=din_i01(end-15:end);
    end
    fprintf(fp,'%s\n',din_i00);
end
fclose(fp);

file1='din_i2.dat';
fp=fopen(file1,'w');
for loop=1:length(din_i2)
    if din_i2(loop)>=0
        din_i00=dec2bin(din_i2(loop),16);
    else
        din_i01=dec2bin(bitxor(abs(din_i2(loop)),2^16-1)+1);%
        din_i00=din_i01(end-15:end);
    end
    fprintf(fp,'%s\n',din_i00);
end
fclose(fp);

file1='din_i3.dat';
fp=fopen(file1,'w');
for loop=1:length(din_i3)
    if din_i3(loop)>=0
        din_i00=dec2bin(din_i3(loop),16);
    else
        din_i01=dec2bin(bitxor(abs(din_i3(loop)),2^16-1)+1);%
        din_i00=din_i01(end-15:end);
    end
    fprintf(fp,'%s\n',din_i00);
end
fclose(fp);

5Aurora接口