HDLBits练习（2）verilog中复制运算的要点

题目：对下面图中每个1位数据进行不同方式Verilog语言中的复制操作，最后输出结果是两者异或

错误操作：

assign out=~{ 5{a}, 5{b}, 5{c}, 5{d}, 5{e} }^{ 5{a,b,c,d,e} };

编译后报错：
Error (10170): Verilog HDL syntax error at top_module.v(9) near text: “,”; expecting “}”. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/h/work/hdlbits.3116519/top_module.v Line: 9
报错内容是在，之前少了一个分号！！！原因是5{a}表示对5个a进行连接，之后的结果是a,a,a,a,a
(！！！注意：这里没有大括号)

之后再与后面5个b相连接时，因该加{}将5个a连接在一起，表示一个整体。正确代码如下

assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}};