UVM——sequence的层次化

sequence的层次化

sequence的层次化包含以下概念：hierarchical sequence；virtual sequence；layering sequence

Hierarchical Sequence

在验证MCDF的寄存器模块时，verifier将SV验证环境进化到了UVM环境之后，关于测试寄存器模块的场景可以将其拆解为：
- 设置时钟和复位
- 测试通道1的控制寄存器和只读寄存器
- 测试通道2的控制寄存器和只读寄存器
- 测试通道3的控制寄存器和只读寄存器

//实例
typedef enum {
   CLKON, CLKOFF, RESET, WRREG, REREG} cmd_t;
class bus_trans extends uvm_sequence_item;
	rand cmd_t cmd;
	rand int addr;
	rand int data;
	constraint cstr{
   
		soft addr == 'h0;
		soft data == 'h0;
	}
	...
endclass

class clk_rst_seq extends uvm_sequence;
	rand int freq;
	...
	task body();
		bus_trans req;
		`uvm_do_with(req, {
   cmd == CLKON; data == freq;})
		`uvm_do_with(req, {
   cmd == RESET; })
	endtask
endclass

class reg_test_seq extends uvm_sequence;
	rand int chnl;
	...
	task body();
		bus_trans req;
		//write and read test for WR register
		`uvm_do_with(req, {
   cmd == WRREG; addr == chnl*'h4;})
		`uvm_do_with(req, {
   cmd == RDREG; addr == chnl*'h4;})
		//read for the RD register
		`uvm_do_with(req, {
   cmd == RDREG; addr == chnl*'h4 + 'h10;})
	endtask
endclass

class reg_test_seq extends uvm_sequence;
	...
	task body();
		clk_rst_seq clkseq;
		reg_test_seq regseq0, regseq1, regseq2;
		//turn on clock with 150Mhz and assert reset
		`uvm_do_with(clkseq, {
   freq == 150;})
		//test the registers of channel0
		`uvm_do_with(regseq0, {
   chnl == 0;})
		//test the registers of channel1
		`uvm_do_with(regseq0, {
   chnl == 1;})
		//test the registers of channel2
		`uvm_do_with(regseq0, {
   chnl == 2;})
	endtask
endclass

class req_master_sequencer extends uvm_sequencer;
	...
endclass

class reg_master_driver extends uvm_driver;
	...
	task run_phase(uvm_phase phase);
		REQ tmp;
		bus_trans req;
		forever begin
			seq_item_port.get_next_item(tmp);
			void'($cast(