乒乓操作
同步FIFO实现乒乓
fifo1进行写,fifo2进行读(第一次没有可读,考虑数据流入的第一个周期很短)
fifo控制模块,写完fifo1指定深度后,拉低写使能,转而拉高fifo2的写使能
两块fifo,前提是一个fifo存储不够,或者写速率大于读速率
module fifo_pingpang(
input rst_n,
input clk,
input [7:0]data_in,
input wr_en,
output reg fifo1_wr_en,
output reg fifo2_wr_en,
output reg fifo1_rd_en,
output reg fifo2_rd_en,
output [7:0]data_out
);
wire [8:0] fifo_cnt1;
wire [8:0] fifo_cnt2;
wire [7:0]data_out1;
wire [7:0]data_out2;
assign data_out=fifo1_rd_en?data_out1:data_out2;
parameter idle = 4'b0000,
start = 4'b0001,
ping = 4'b0010,
pang = 4'b0100;
reg[3:0]state;
reg[3:0]next_state;
//
always@(posedge clk or negedge rst_n)begin
if(!rst_n) state<= idle;
else state <= next_state;
end
//
always@(posedge clk)begin
case(state)
idle:if(wr_en)
next_state <= start;
else next_state <= idle;
start:if(fifo_cnt1 == 9'd500)
next_state <= ping;
else next_state <= start;
ping:if(fifo_cnt2 == 9'd500)
next_state <= pang;