FPGA IMPLEMENT 1Gb/10Gb ETH（二.2）

    // calculate the running disparity after the 5B6B block encode 根据输入的rd和数据5b，计算出6b输出
always@(posedge clk)
begin
   if(rst)
    b6 <= 0;
   else begin
   if (k28)   begin                        //K.28
     if (!disparity_pos_in)
             b6 <= 6'b111100;
     else
             b6 <= 6'b000011;
	 end
   else
     case (d8[4:0])
             5'b00000 :                 //D.0
               if (disparity_pos_in)
                     b6 <= 6'b000110;
               else
                     b6 <= 6'b111001;
             5'b00001 :                 //D.1
               if (disparity_pos_in)
                     b6 <= 6'b010001;
               else
                     b6 <= 6'b101110;
             5'b00010 :                 //D.2
               if (disparity_pos_in)
                     b6 <= 6'b010010;
               else
                     b6 <= 6'b101101;