FPGA IMPLEMENT 1Gb/10Gb ETH（二.3）

   // reverse the bits
   genvar i;
   generate q6_loop
   for (I <= 0; I < 6; I <= I + 1)
     assign q10[I] = b6[I];
   endgenerate 

   // calculate the running disparity after the 5B6B block encode 计算6b的输出极性
always@(posedge clk)
begin
   if(rst)
	 pdes6 <=disparity_pos_in;
   else 
   if (k28)
     pdes6 <= !disparity_pos_in;
   else
     case (d8[4:0])
             5'b00000 : pdes6 <= !disparity_pos_in;
             5'b00001 : pdes6 <= !disparity_pos_in;
             5'b00010 : pdes6 <= !disparity_pos_in;
             5'b00011 : pdes6 <= disparity_pos_in;
             5'b00100 : pdes6 <= !disparity_pos_in;
             5'b00101 : pdes6 <= disparity_pos_in;
             5'b00110 : pdes6 <= disparity_pos_in;
             5'b00111 : pdes6 <= disparity_pos_in;
             5'b01000 : pdes6 <= !disparity_pos_in;
             5'b01001 : pdes6 <= disparity_pos_in;
             5'b01010 : pdes6 <= disparity_pos_in;
             5'b01011 : pdes6 <= disparity_pos_in;
             5'b01100 : pdes6 <= disparity_pos_in;
             5'b01101 : pdes6 <= disparity_pos_in;
             5'b01110 : pdes6 <= disparity_pos_in;
             5'b01111 : pdes6 <= !disparity_pos_in;
             5'b10000 : pdes6 <= !disparity_pos_in;
             5'b10001 : pdes6 <= disparity_pos_in;
             5'b10010 : pdes6 <= disparity_pos_in;
             5'b10011 : pdes6 <= disparity_pos_in;
             5'b10100 : pdes6 <= disparity_pos_in;
             5'b10101 : pdes6 <= disparity_pos_in;
             5'b10110 : pdes6 <= disparity_pos_in;
             5'b10111 : pdes6 <= !disparity_pos_in;
             5'b11000 : pdes6 <= !disparity_pos_in;
             5'b11001 : pdes6 <= disparity_pos_in;
             5'b11010 : pdes6 <= disparity_pos_in;
             5'b11011 : pdes6 <= !disparity_pos_in;
             5'b11100 : pdes6 <= disparity_pos_in;
             5'b11101 : pdes6 <= !disparity_pos_in;
             5'b11110 : pdes6 <= !disparity_pos_in;
             5'b11111 : pdes6 <= !disparity_pos_in;
             default  : pdes6 <= disparity_pos_in;
     endcase // case(d8[4:0])
end

always@(posedge clk)//根据输出6b的极性和输入数据的d3，计算输出的4b输出
begin
   if(rst)
	b4 <= 0；
   else case (d8[7:5])
     3'b000 :                     //D/K.x.0
             if (pdes6)
               b4 <= 4'b0010;
       else
               b4 <= 4'b1101;
     3'b001 :                     //D/K.x.1
             if (k28 && !pdes6)
               b4 <= 4'b0110;
             else
               b4 <= 4'b1001;
     3'b010 :                     //D/K.x.2
             if (k28 && !pdes6)
               b4 <= 4'b0101;
             else
               b4 <= 4'b1010;
     3'b011 :                     //D/K.x.3
             if (!pdes6)
               b4 <= 4'b0011;
             else
               b4 <= 4'b1100;
     3'b100 :                     //D/K.x.4
             if (pdes6)
               b4 <= 4'b0100;
             else
               b4 <= 4'b1011;
     3'b101 :                     //D/K.x.5
             if (k28 && !pdes6)
               b4 <= 4'b1010;
             else
               b4 <= 4'b0101;
     3'b110 :                     //D/K.x.6
             if (k28 && !pdes6)
               b4 <= 4'b1001;
             else
               b4 <= 4'b0110;
     3'b111 :                     //D.x.P7
             if (!a7)
                 if (!pdes6)
                 b4 <= 4'b0111;
                           else
                 b4 <= 4'b1000;
             else                   //D.y.A7 K28.7
                 if (!pdes6)
                 b4 <= 4'b1110;
                           else
                 b4 <= 4'b0001;
     default :
             b4 <= 4'bXXXX;
   endcase
end
   // Reverse the bits
   generate q4_loop
   for (I <= 0; I < 4; I <= I + 1)
    assign  q10[I+6] = b4[I];
   endgenerate

always@(posedge clk)   // Calculate the running disparity after the 4B group 输出极性
begin
   if(rst)
	disparity_pos_out<=pdes6;
   else 
   case (d8[7:5])
     3'b000  : disparity_pos_out <= ~pdes6;
     3'b001  : disparity_pos_out <= pdes6;
     3'b010  : disparity_pos_out <= pdes6;
     3'b011  : disparity_pos_out <= pdes6;
     3'b100  : disparity_pos_out <= ~pdes6;
     3'b101  : disparity_pos_out <= pdes6;
     3'b110  : disparity_pos_out <= pdes6;
     3'b111  : disparity_pos_out <= ~pdes6;
     default : disparity_pos_out <= pdes6;
   endcase
end

endmodule