FPGA IMPLEMENT 1Gb/10Gb ETH（二.4）

decode 8b/10b 代码更简单，因为对应关系简单：

   module decode_8b10b(
	  input clk,
	  input rst,
      input  [0:9] d10,
      output reg[7:0] q8,
      output       is_k)
      wire          k28;
      wire    [9:0] d10_rev;
	  
      genvar I;
	  generate reverse_loop
	   // reverse the 10B codeword
	   for (I = 0; I < 10; I = I + 1)
		 assign d10_rev[I] = d10[I];
	  endgenerate 
	 
	always@(posedge clk)
	begin
		if(rst)
			q8[4:0] <= 5'b11110;
		else 
		   case (d10_rev[5:0])
			 6'b000110 : q8[4:0] <= 5'b00000;   //D.0
			 6'b111001 : q8[4:0] <= 5'b00000;   //D.0
			 6'b010001 : q8[4:0] <= 5'b00001;   //D.1
			 6'b101110 : q8[4:0] <= 5'b00001;   //D.1
			 6'b010010 : q8[4:0] <= 5'b00010;   //D.2
			 6'b101101 : q8[4:0] <= 5'b00010;   //D.2
			 6'b100011 : q8[4:0] <= 5'b00011;   //D.3
			 6'b010100 : q8[4:0] <= 5'