FPGA学习笔记18--8位加法器

module add8(           //待测试的 8位加法器模块 

output[7:0] SUM, 

output cout, 

input[7:0] A,B,

input cin
);
assign {cout,SUM}=A+B+cin; 

endmodule 

`timescale 1ns/1ns 

module add8_tp;                           //仿真模块无端口列表 

reg[7:0] A,B;                             //输入激励信号定义为 reg型 

reg cin; 

wire[7:0] SUM;                            //输出信号定义为wire型 

wire cout; 

parameter DELY = 100; 

add8 AD1(SUM,cout,A,B,cin);              //调用测试对象 

initial begin                             //激励波形设定 

          A= 8'd0;      B= 8'd0;     cin=1'b0; 

#DELY     A= 8'd100;    B= 8'd200;   cin=1'b1; 

#DELY     A= 8'd200;    B= 8'd88; 

#DELY     A= 8'd210;    B= 8'd18;    cin=1'b0; 

#DELY     A= 8'd12;     B= 8'd12; 

#DELY     A= 8'd100;    B= 8'd154; 

#DELY     A= 8'd255;    B= 8'd255;   cin=1'b1; 

#DELY     $finish; 

end

endmodule