40--基本D触发器

module DFF(q,d,clk);
output q;
reg q;
input d,clk;
always @(posedge clk )
	begin
	q<=d;
	end
endmodule

module tb_DFF();
wire q;
reg clk,d;
DFF u1(.q(q),.clk(clk),.d(d));
initial begin
clk<=1'b0;
d<=1'b1;
end
always #5 clk<=~clk;
always #50 d<=~d;
endmodule