【HDLBits刷题】Countslow.

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.

 

Module Declaration

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);

设计一个0～9的计数器，共10个周期。该计数器采用同步复位且复位为0。但是本题是希望该计数器并不是随着clk的变化而递增，而是随着一个slowena使能信号来控制增加。时序图如下图所示

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
    always @ (posedge clk)
        begin
            if(reset)
                q <= 4'b0000;
            else if(q >= 4'b1001 && slowena)
                q <= 4'b0000;
            else if(slowena)
                q <= q + 1'b1;
            else
                q <= q; 
        end

endmodule

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);

    reg [3:0] cnt;
    //period is 10 
    //What is supposed to happen when the counter is 9 and not enabled?
    always @ (posedge clk)
        begin
            if(reset)
                cnt <= 4'b0;
            else if(slowena == 1'b1)
                //slowena 为高，计数器才能正常运行
                begin
                    if(cnt == 4'd9)
                        cnt <= 4'b0;
                    //因为题目要求周期为10，所以0～9之后下一个为0；
                    else 
                        cnt <= cnt + 4'd1;
                end
        end

    assign q = cnt;

endmodule