HDLbits--countslow

题目描述：一个十进制计数器，当slowena为1时开始计数，当slowena为0时保存当前状态。所有状态的改变在时钟上升沿有效。

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
    
    reg [3:0] count;

    initial
        count = 0;
    always@(posedge clk)
        begin
            if(reset)
                count <= 0;
            else if((slowena)&&(count<4'b1001))
                count <= count+1'b1;
            else if((!slowena))
                count <= count;
            else
                count =0;
        end
    assign q= count;

endmodule