HDLBits练习-有限状态机(FSM)（2）

HDLBits练习

Circuits-Sequential Logic-Finite State Machines（2）

题9：Design a Moore FSM

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    reg [2:0]state,next_state;
    always@(posedge clk)begin
        if(reset)
            state<=3'b000;
        else 
            state<=next_state;
    end
    
    always@(*)begin
        case(state)
            3'b000:begin//最低点
                case(s[1])
                    0:next_state=3'b000;
                    1:next_state=3'b001;
                endcase
            end
            3'b001:begin//上升至1、2中间
                casez({s[2],s[1]})
                    2'b1z:next_state=3'b011;
                    2'b01:next_state=3'b001;
                    2'b00:next_state=3'b000;
                endcase
            end
            3'b010:begin//下降至1、2中间
                casez({s[2],s[1]})
                    2'b1z:next_state=3'b011;
                    2'b01:next_state=3'b010;
                    2'b00:next_state=3'b000;
                endcase
            end
            3'b011:begin//上升至2、3之间
                casez({s[3],s[2]})
                    2'b1z:next_state=3'b111;
                    2'b01:next_state=3'b011;
                    2'b00:next_state=3'b010;
                endcase
            end
            3'b100:begin//下降至2、3之间
                casez({s[3],s[2]})
                    2'b1z:next_state=3'b111;
                    2'b01:next_state=3'b100;
                    2'b00:next_state=3'b010;
                endcase
            end
            3'b111:begin//最高点
                case(s[3])
                    1:next_state=3'b111;
                    0:next_state=3'b100;
                endcase
            end
            default:next_state='dx;
        endcase
    end
    assign fr1=(state!=3'b111);
    assign fr2=(state==3'b000 | state==3'b001 | state==3'b010);
    assign fr3=(state==3'b000);
    assign dfr=(state==3'b000 | state==3'b010 | state==3'b100);
endmodule

题10：Lemmmings 1

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right); //  

    // parameter LEFT=0, RIGHT=1, ...
    reg state, next_state;

    always @(*) begin
        // State transition logic
        state=next_state;
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)begin 
            next_state<=1;
        end
        else begin
            case({bump_left,bump_right})
                2'b00:next_state=state;
                2'b01:next_state=1;
                2'b10:next_state=0;
                2'b11:next_state=!state;
            endcase
        end
    end

    // Output logic
    assign walk_left = (state == 1);
    assign walk_right = (state == 0);

endmodule

题11：Lemmings 2

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
    reg [1:0] state,next_state;
 
    always@(posedge clk or posedge areset)begin        
        if(areset)
            state<=2'b00;
        else
            state<=next_state;
    end       
    
    always@(*)begin
        case(state)
            2'b00:begin//向左走
                if(ground==0)
                    next_state=2'b10;
                else begin
                    casez({bump_left,bump_right})
                        2'b1z:next_state=2'b01;
        				2'b0z:next_state=2'b00;
                    endcase
                end
            end
            2'b01:begin//向右走
                if(ground==0)
                    next_state=2'b11;
                else begin
                    casez({bump_left,bump_right})
                        2'bz1:next_state=2'b00;
        				2'bz0:next_state=2'b01;
                    endcase
                end
            end
            2'b10:begin//记录状态
                if(ground==0)
                    next_state=2'b10;
                else
                    next_state=2'b00;
            end
            2'b11:begin//记录状态
                if(ground==0)
                    next_state=2'b11;
                else
                    next_state=2'b01;
            end
        endcase
    end
                    
    assign walk_left=(state==2'b00);
    assign walk_right=(state==2'b01);
    assign aaah=(state==2'b10 | state==2'b11);
endmodule 

题12：Lemmings 3

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    reg [2:0]state,next_state;
    always@(*)begin
        case(state)
            3'b000:begin//向左走
                if(ground==0)
                    next_state=3'b010;
                else begin
                    casez({dig,bump_left,bump_right})
                        3'b1zz:next_state=3'b100;
                        3'b01z:next_state=3'b001;
                        3'b00z:next_state=3'b000;
                    endcase
                end
            end
            3'b001:begin//向右走
                if(ground==0)
                    next_state=3'b011;
                else begin
                    casez({dig,bump_left,bump_right})
                        3'b1zz:next_state=3'b101;
                        3'b0z1:next_state=3'b000;
                        3'b0z0:next_state=3'b001;
                    endcase
                end
            end  
            3'b010:begin//降落向左走
                if(ground==0)
                    next_state=3'b010;
                else begin
                    next_state=3'b000;
                end
            end
            3'b011:begin//降落向右走
                if(ground==0)
                    next_state=3'b011;
                else begin
                    next_state=3'b001;
                end
            end     
            3'b100:begin//向左挖
                if(ground==0)
                    next_state=3'b010;
                else begin
                    next_state=3'b100;
                end
            end           
            3'b101:begin//向右挖
                if(ground==0)
                    next_state=3'b011;
                else begin
                    next_state=3'b101;
                end
            end    
        endcase
    end
    always@(posedge clk or posedge areset)begin
        if(areset)
            state=3'b000;
        else
            state=next_state;
    end
    assign walk_left=(state==3'b000);
    assign walk_right=(state==3'b001);
    assign aaah=(state==3'b010 | state==3'b011);    
    assign digging=(state==3'b100 | state==3'b101); 
endmodule

题13：Lemmings 4

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
    integer c;
    reg dec;
    reg [2:0]state,next_state;
    always@(*)begin
        case(state)
            3'b000:begin//向左走
                if(ground==0)
                    next_state=3'b010;
                else begin
                    casez({dig,bump_left,bump_right})
                        3'b1zz:next_state=3'b100;
                        3'b01z:next_state=3'b001;
                        3'b00z:next_state=3'b000;
                    endcase
                end
            end
            3'b001:begin//向右走
                if(ground==0)
                    next_state=3'b011;
                else begin
                    casez({dig,bump_left,bump_right})
                        3'b1zz:next_state=3'b101;
                        3'b0z1:next_state=3'b000;
                        3'b0z0:next_state=3'b001;
                    endcase
                end
            end  
            3'b010:begin//降落向左走
                if(ground==0)begin
                    next_state=3'b010;
                end
                else begin
                    next_state=(c>20)?3'b111 : 3'b000;
                end
            end
            3'b011:begin//降落向右走
                if(ground==0)begin
                    next_state=3'b011;
                end
                else begin
                    next_state=(c>20)?3'b111 : 3'b001;
                end
            end     
            3'b100:begin//向左挖
                if(ground==0)
                    next_state=3'b010;
                else begin
                    next_state=3'b100;
                end
            end           
            3'b101:begin//向右挖
                if(ground==0)
                    next_state=3'b011;
                else begin
                    next_state=3'b101;
                end
            end 
            3'b111:begin//死亡
                next_state=3'b111;
            end
        endcase
    end
    
    always@(posedge clk or posedge areset)begin
        if(areset)
            c<=0;
        else begin
            if(ground==0)
                c<=c+1'b1;
            else 
                c<=0;
        end
    end
    
    always@(posedge clk or posedge areset)begin
        if(areset)
            state=3'b000;
        else
            state=next_state;
    end
    
    assign walk_left=(state==3'b000);
    assign walk_right=(state==3'b001);
    assign aaah=(state==3'b010 | state==3'b011);    
    assign digging=(state==3'b100 | state==3'b101); 
endmodule