HDLBits练习-有限状态机(FSM)（4）

HDLBits练习

Circuits-Sequential Logic-Finite State Machines（4）

题20：Sequence recognition

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err
    );
    reg [3:0]state,next_state;
    always@(posedge clk)begin
        if(reset)
            state<= 4'd0;
            else begin
                state<=next_state;
            end
    end

    always@(*)begin
        case(state)
        4'd0:begin//0
            case(in)
            0:next_state=4'd0;
            1:next_state=4'd1;
            endcase
        end
        4'd1:begin//01
            case(in)
            0:next_state=4'd0;
            1:next_state=4'd2;
            endcase
        end
        4'd2:begin//011
            case(in)
            0:next_state=4'd0;
            1:next_state=4'd3;
            endcase
        end
        4'd3:begin//0111
            case(in)
            0:next_state=4'd0;
            1:next_state=4'd4;
            endcase
        end
        4'd4:begin//01111
            case(in)
            0:next_state=4'd0;
            1:next_state=4'd5;
            endcase
        end
        4'd5:begin//011111 
            case(in)
            0:next_state=4'd8;
            1:next_state=4'd6;
            endcase
        end
        4'd6:begin//0111111 
            case(in)
            0:next_state=4'd9;
            1:next_state=4'd7;
            endcase
        end
        4'd7:begin//err
            case(in)
            0:next_state=4'd0;
            1:next_state=4'd7;
            endcase
        end
        4'd8:begin//disc
            case(in)
            0:next_state=4'd0;
            1:next_state=4'd1;
            endcase
        end
        4'd9:begin//flag
            case(in)
            0:next_state=4'd0;
            1:next_state=4'd1;
            endcase
        end
        endcase
    end
    assign disc=(state==4'd8);
    assign flag=(state==4'd9);
    assign err=(state==4'd7);
endmodule

题21: Q8: Design a Mealy FSM

    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
    reg [1:0]state,next_state;
    always@(posedge clk or negedge aresetn)begin
        if(!aresetn)
            state<=2'd3;
            else
            state<=next_state;
    end
    always@(*)begin
        case(state)
        2'd0:begin//1
        case(x)
        0:next_state=2'd1;
        1:next_state=2'd0;
        endcase
        end
        2'd1:begin//10
        case(x)
        0:next_state=2'd3;
        1:next_state=2'd2;
        endcase
        end
        2'd2:begin//101
        case(x)
        0:next_state=2'd1;
        1:next_state=2'd0;
        endcase
        end
        2'd3:begin//100..
        case(x)
        0:next_state=2'd3;
        1:next_state=2'd0;
        endcase
        end
        endcase
    end
    assign z=(next_state==2'd2);
endmodule

题22: Q5a: Serial two’s complementer (Moore FSM)

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    reg [1:0]state,next_state;
    reg dx;
    always@(posedge clk or posedge areset)begin
        if(areset)
            state<=2'd0;
            else
            state<=next_state;
    end
    always@(*)begin
        case(state)
        2'd0:begin//进位
            case(x)
            0:next_state=2'd0;
            1:next_state=2'd1;
            endcase
        end
        2'd1:next_state=2'd2;//进位停止
        2'd2:next_state=2'd2;//取反
        endcase
    end
    always@(posedge clk)begin
        dx<=x;
    end
    assign z=(state==2'd0)? 0 : ((state==2'd1)? 1 : !dx);
endmodule

题23：Q5b: Serial two’s complementer (Mealy FSM)

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    reg state,next_state;//A=0;B=1;
    always@(posedge clk or posedge areset)begin
        if(areset)
            state<=0;
        else
            state<=next_state;
    end
    always@(*)begin
        case(state)
            0:begin
                case(x)
                0:begin 
                    next_state=0;
                    z=0;
                end
                1:begin
                    next_state=1;
                    z=1;
                end
                endcase
            end
            1:begin
                case(x)
                0:begin 
                    next_state=1;
                    z=1;
                end
                1:begin
                    next_state=1;
                    z=0;
                end
                endcase
            end
        endcase
    end
endmodule

题24：Q3a: FSM

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);
reg state,next_state;
always@(posedge clk)begin
    if(reset)
    state<=0;
    else
    state<=next_state;
end
always@(*)begin
    case(state)
    0:begin//A
        case(s)
        1:next_state=1;
        0:next_state=0;
        endcase
    end
    1:next_state=1;//B
    endcase
end
reg [1:0]c,n;
always@(posedge clk)begin
    if(state==0)begin
        c<=2'd0;n<=2'd0;
    end
    else begin
        c<=(c==2'd2)? 2'd0 : c+1'b1;
        if(c==2'd0)begin
            n<=(w==1)? 2'd1 : 2'd0;
        end
        else begin
            n<=(w==1)? n+1'b1 : n;
        end
    end
end
assign z=(c==2'd0 & n==2'd2 & state==1)?1:0;
endmodule