HDLBits练习-Finding bugs in code

HDLBits练习

Verification:Reading Simulations-Finding bugs in code

题1：Mux

module top_module (
    input sel,
    input [7:0] a,
    input [7:0] b,
    output [7:0]out  );

    assign out = (sel)? a : b;

endmodule

题2：NAND

module top_module (input a, input b, input c, output out);//
	wire dout;
    andgate inst1 (.out(dout),.a(a),.b(b),.c(c),.d(1),.e(1));
	assign out=~dout;
endmodule

题3：Mux

module top_module (
    input [1:0] sel,
    input [7:0] a,
    input [7:0] b,
    input [7:0] c,
    input [7:0] d,
    output [7:0] out  ); //

    wire [7:0]mux0, mux1;
    mux2 u0 (.sel(sel[0]), .a(a), .b(b), .out(mux0) );
    mux2 u1 (.sel(sel[0]), .a(c), .b(d), .out(mux1) );
    mux2 u2 (.sel(sel[1]), .a(mux0), .b(mux1), .out(out) );
    
endmodule

题4：Add/sub

// synthesis verilog_input_version verilog_2001
module top_module ( 
    input do_sub,
    input [7:0] a,
    input [7:0] b,
    output reg [7:0] out,
    output result_is_zero
);//
    
    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
        endcase
    end
    assign result_is_zero = (out==8'd0);
    
endmodule

题5：Case statement

module top_module (
    input [7:0] code,
    output reg [3:0] out,
    output reg valid);//

     always @(*) begin
         case (code)
            8'h45: out = 4'd0;
            8'h16: out = 4'd1;
            8'h1e: out = 4'd2;
            8'h26: out = 4'd3;
            8'h25: out = 4'd4;
            8'h2e: out = 4'd5;
            8'h36: out = 4'd6;
            8'h3d: out = 4'd7;
            8'h3e: out = 4'd8;
            8'h46: out = 4'd9;
            default: begin
                out = 4'd0;
            end
        endcase

         if(out == 4'd0 && code!= 8'h45) begin
            valid = 1'b0;
        end
        else begin
            valid = 1'b1;
        end
     end
     		              
endmodule