HDLBits 答案之rule90

答案如下，谷歌翻译成中文会有一定偏差，建议阅读原文题目

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 

    
    always @(posedge clk) begin
        if (load) 
        q<=data;
        else begin
            for (int i=1;i<511;i=i+1) begin
                q[i]<=q[i+1]^q[i-1];
                q[0]<=q[1]^1'b0;
                q[511]<=q[510]^1'b0;
            end
        end
    end
        
endmodule