多加一个数据路径。先用三个寄存器寄存一下输入,然后assign组合一下。
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done); //
parameter b1=0,b2=1,b3=2,d=3;
reg [1:0] state,nstate;
reg [7:0] m1,m2,m3;
always @(posedge clk) begin
if (reset)
state<=b1;
else
state<=nstate;
end
always @(*) begin
case(state)
b1: nstate=in[3]?b2:b1;
b2: nstate=b3;
b3: nstate=d;
d: nstate=in[3]?b2:b1;
default nstate=b1;
endcase
end
always @(posedge clk) begin
if (reset)
m1<=7'b0;
else if (nstate==b2)
m1<=in;
else
m1<=m1;
end
always @(posedge clk) begin
if (reset)
m2<=7'b0;
else if (nstate==b3)
m2<=in;
else
m2<=m2;
end
always @(posedge clk) begin
if (reset)
m3<=7'b0;
else if (nstate==d)
m3<=in;
else
m3<=m3;
end
assign done=(state==d);
assign out_bytes={m1,m2,m3};
endmodule