verilog中unsigned与signed加法结果的比较（带源码）

根据仿真结果可以知道，结果是完全相同的。

源代码：

module symbexam(
	//input 
	d1,
	d2,
	//output
	signed_out,
	unsigned_out
);
input	[3:0]	d1;
input 	[3:0]	d2;
output 	[4:0] 	unsigned_out;
output 	signed [4:0] 	signed_out;
//unsigned add;
assign unsigned_out = d1+d2;
//signed add;
wire signed [3:0] s_d1;
wire signed [3:0] s_d2;
assign s_d1 = d1;
assign s_d2 = d2;
assign signed_out = s_d1 + s_d2;

endmodule

测试代码：

`timescale 1ns/1ns 
module tb_symbexam();
//input
reg [3:0]d1;
reg [3:0]d2;
//output
wire signed [4:0]signed_out;
wire [4:0]unsigned_out;
//main code
initial
	begin
		d1 = 4'b0011;
		d2 = 4'b0111;
		#20
		d1 = 4'b1011;
		d2 = 4'b1111;
		#20 $stop;
	end
//symbexam instance
symbexam u0_symbexam(
	.d1(d1),
	.d2(d2),
	.signed_out(signed_out),
	.unsigned_out(unsigned_out)
);
endmodule

仿真结果：