本文详细介绍了Verilog中表达式类型的确定规则，包括十进制数是有符号的，基于基数的数字（除非使用`s`符号）是无符号的，位选择结果和部分选择结果都是无符号的，比较结果也是无符号的。同时，涉及实数的运算结果为实数，无符号运算结果保持无符号，而有符号运算在扩展宽度时若符号位为`X`或`Z`，则会填充`X`或`Z`。赋值操作时，如果右操作数宽度大于左操作数，高位会被截断，且不强制警告或报告大小不匹配错误。举例说明了不同类型变量赋值后的结果变化。
the following are the rules for determining the resulting type of an expression
-----expression type depends only on the oprands .It does not depend on the left-hand(if any)
-----decimal numbers are signed
-----based_numbers are unsigned,except where the s notation is used in the based specifier
-----bit-select results are unsigned , regardless of the oprands
-----part-select results are unsigned ,regradless of oprands
-----part-select results are unsigned regardless of the oprands even if the part-select specifes the entire vector
reg [15:0] a;
reg signed [7:0] b;
initial
a = b[7:0]; // b[7:0] is unsigned and therefore zero-extended
-----concatenate result are unsigned regtadless of the oprands
-----comparison results (1,0) are unsigned regradless of the oprands
-----reals converted to integers by type coercion are signed
-----the sign and size of any self-determine
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