串行数据检测电路Verilog HDL语言描述，（阎石课后题6.35）

`timescale 1 ns/1 ps
module Exercises6_35(CLK,RESET,M1,M2,Y,state);
input CLK;
input RESET;
input M1,M2;
output [1:0]state;
output Y;
//Frequency divide
reg[22:0]cnt1;
reg CLK_c;
always@(posedge CLK or negedge RESET)
if(!RESET)
begin
cnt1<=1’b0;
CLK_c<=1’b0;
end
else
if(cnt110000)
begin
CLK_c<=~CLK_c;
cnt1<=0;
end
else
cnt1<=cnt1+1’b1;
//M1 M2 key eliminate jitter
reg M1_en,M2_en,pos;
reg[8:0]cnt2;
always@(posedge CLK_c or negedge RESET)
if(!RESET)
begin
pos<=0;
M1_en<=0;
M2_en<=0;
cnt2<=0;
end
else
begin
cnt2<=cnt2+1’b1;
if(!M1)
begin
if(cnt210 && pos0)
begin
M1_en<=1;
end
else if(cnt2200)
begin
pos<=1;
end
else if(cnt2202)
begin
M1_en<=0;
end
end
else if(!M2)
begin
if(cnt210 && pos0)
begin
M2_en<=1;
end
else if(cnt2200)
begin
pos<=1;
end
else if(cnt2==202)
begin
M2_en<=0;
end
end
else
begin
pos<=0;
M1_en<=0;
M2_en<=0;
cnt2<=0;
end
end
//4-State Mealy state machine
reg reg_out;
reg[1:0]state;
parameter S0=2’b00,S1=2’b01,S2=2’b10,S3=2’b11;
always@(posedge CLK_c or negedge RESET)
if(!RESET)
begin
state<=S0;
end
else
case(state)
S0:
if(M1_en)
state<=S1;
else
state<=S0;
S1:
if(M1_en)
state<=S2;
else if(M2_en)
state<=S0;
else
state<=S1;
S2:
if(M1_en)
state<=S3;
else if(M2_en)
state<=S0;
else
state<=S2;
S3:
if(M1_en)
state<=S0;
else
state<=S3;
endcase
always@(state or M1_en or pos)
begin
case(state)
S3:
if(M1_en && !pos)
begin
reg_out<=1’b1;
end
default:
begin
reg_out<=1’b0;
end
endcase
end
assign Y=reg_out;
endmodule