timing-output delay

vivado timing constrains wizard-output delay

内容链接：https://forums.xilinx.com/t5/Implementation/What-do-trce-dly-max-and-trce-dly-min-mean-when-setting-output/m-p/941509
Re: What do trce_dly_max and trce_dly_min mean when setting output delay constraints?

gle-data-rate (SDR) output from the FPGA. One way to think about the problem is that this is simply the transfer of data from a register located inside the FPGA to a register located outside the FPGA.
We can tackle analysis of the problem by first drawing a picture of the essential circuits and label the timing-arcs.

In the picture above, data is being transferred from the register, DAT1_reg, inside the FPGA to the external register, EX1_reg. Throughout the diagram, I have drawn timing-arcs that identify signal propagation delay. For example, t_mcd, is the delay of the clock signal, CLK, that travels from the MMCM clock generator to