2021-08-17

Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input called resetn.

The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).

(The original exam question asked for a state diagram only. But here, implement the FSM.)

下面展示一些 内联代码片。

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    reg [3:0]state,n_state;
    parameter A=0,B=1,C=2,D=3,E=4,F=5,G=6,P0=7,P1=8;
    //P0代表永久g=0，P1代表永久g=1
    //状态转化
    always@(posedge clk)begin
        if(~resetn)begin
            state <= A;
        end
        else begin
            state <= n_state;
        end
    end
    //状态转化的条件
    always@(*)begin
        case(state)
            A: n_state = B;
            B: n_state = C;
            C: n_state = x? D:C;
            D: n_state = x? D:E;
            E: n_state = x? F:C;
            F: n_state = y? P1:G;
            G: n_state = y? P1:P0;
            P1: n_state = P1;
            P0: n_state = P0;
        endcase
    end
    assign f = state==B,
        g = state==F||state==P1||state==G;

endmodule