HDLBits：状态机之“Q2b: Another FSM”

最新推荐文章于 2023-08-11 13:51:37 发布

ZeldaL

最新推荐文章于 2023-08-11 13:51:37 发布

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分类专栏：数电基础、Verilog 文章标签： verilog

本文链接：https://blog.csdn.net/ZeldaL/article/details/124339561

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本文解析了一个用于电机控制的有限状态机(FSM)，它接收输入x和y，根据特定规则设置输出f和g。FSM在重置后首先设置f为1，随后检测x的101序列，y的1信号触发g状态变化。关键代码展示了如何通过状态转换和条件判断来实现这些功能。

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题链接： Exams/2013 q2bfsm - HDLBits (01xz.net)

题目：

Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input called resetn.

The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).

注意题中着重点：

“Then”表示到达B状态（f=1）后，再过一个状态才开始检测“101”序列；
末尾两句的翻译理解：两个周期内有“y=1”（无论1个还是2个）则保持“g=1”，全为“y=0”则保持“g=0”；且在这两个“判断周期”内 g 的输出也是1（"While maintaining g = 1 the FSM has to monitor the y input."意味着E状态“g=1”）。

代码如下：

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output f,
    output g
); 
    parameter A=0, B=1, C=2, D1=3, D2=4, D3=5, E=6, KEEP_1=7, KEEP_0=8;
    reg [3:0] state, next_state;
    
    always @(*) begin
        case(state)
            A: next_state = B;
            B: next_state = C;
            C: next_state = x ? D1:C;
            D1: next_state = x ? D1:D2;
            D2: next_state = x ? D3:C;
            D3: next_state = y ? KEEP_1:E;
            E: next_state = y ? KEEP_1:KEEP_0;
			KEEP_1: next_state = KEEP_1;
            KEEP_0: next_state = KEEP_0;
            default: next_state = A;
        endcase
    end
    
    always @(posedge clk) begin
        if(~resetn) state <= A;
        else state <= next_state;
    end
    
    assign f = (state==B);
    assign g = (state==D3) || (state==E) || (state==KEEP_1);

endmodule